Details of the instruction cache included in the nrf52840

[FormerMember]

Hello everyone,

I read in the datasheet of the nrf52840 that an instruction cache is included in the chip, but I couldn't find details about it (i.e. its architecture, consisting of how many lines, of which size, the replacement logic and so on). Is there some documentation about this?

Thanks a lot.

[Håkon Alseth]

Hi,

 

The i-cache is an instruction cache, and the behavior is explained here:

https://docs.nordicsemi.com/bundle/ps_nrf52840/page/nvmc.html#ariaid-title9

Which is 2048 bytes:

https://docs.nordicsemi.com/bundle/ps_nrf52840/page/nvmc.html#ariaid-title24

 

Kind regards,

Håkon