QSPI does not work in quad mode

[Doug K]

Hello,

I am using the NRF52840 with the flash chip W25Q32. I tried using the sample program "Flash Sample" with my device set in qspi. I can get the flash device reading and writing when I use:

writeoc = "pp";  
readoc = "fastread";  

It fails when using quad I/O. I noticed that the Quad enable bit is different for when using the W25Q32 vs the one MX flash used on the dev kits. Does this need to be set?

&qspi {
    status = "okay";
    pinctrl-0 = <&qspi_default>;
    pinctrl-1 = <&qspi_sleep>;
    pinctrl-names = "default", "sleep";
    w25q32: w25q32jv@0 {
        compatible = "nordic,qspi-nor";
        reg = <0>;
        writeoc = "pp4io";    // Quad Input Page Program
        readoc = "read4io";   // Fast Read Quad I/O
        sck-frequency = <8000000>; // 8MHz SPI clock
        jedec-id = [EF 40 16];  // Manufacturer and device ID
        size = <33554432>;  // 4MB (32Mb)
        has-dpd;
        t-enter-dpd = <10000>;  // Enter Deep Power Down time (10µs)
        t-exit-dpd = <35000>;   // Exit Deep Power Down time (35µs)
    };
};

Is there flash command to read and write the status registers so I can set them myself?

Thanks

[Sigurd Hellesvik]

Hi,

Try the JESD216 sample. This can read out JEDEC info from the external flash, helping you write the DTS file.

Does it help to update the DTS after this sample?

Regards,
Sigurd Hellesvik

[Doug K]

Here was the printout from JESD216 sample:

w25q32jv@0: SFDP v 1.5 AP ff with 1 PH
PH0: ff00 rev 1.5: 16 DW @ 80
Summary of BFP content:
DTR Clocking supported
Addressing: 3-Byte only
4-KiBy erase: uniform
Support QSPI XIP
Support 1-1-1
Support 1-1-2: instr 3Bh, 0 mode clocks, 8 waits
Support 1-1-4: instr 6Bh, 0 mode clocks, 8 waits
Support 1-2-2: instr BBh, 2 mode clocks, 2 waits
Support 1-4-4: instr EBh, 2 mode clocks, 4 waits
Support 4-4-4: instr EBh, 2 mode clocks, 0 waits
Flash density: 4194304 bytes
ET1: instr 20h for 4096 By; typ 64 ms, max 896 ms
ET2: instr 52h for 32768 By; typ 128 ms, max 1792 ms
ET3: instr D8h for 65536 By; typ 160 ms, max 2240 ms
Chip erase: typ 12000 ms, max 72000 ms
Byte program: type 32 + 3 * B us, max 192 + 18 * B us
Page program: typ 704 us, max 4224 us
Page program size: 256 By
Suspend: 75h ; Resume: 7Ah
DPD: Enter B9h, exit ABh ; delay 3000 ns ; poll 0x3d
HOLD or RESET Disable: unsupported
QER: 4
0-4-4 Mode methods: entry 0xd ; exit 0x3d
4-4-4 Mode sequences: enable 0x11 ; disable 0x9
Soft Reset and Rescue Sequence support: 0x30
Status Register 1 support: 0x69
size = <33554432> bits;
sfdp-bfp = [
    e5 20 f9 ff  ff ff ff 01  44 eb 08 6b  08 3b 42 bb
    fe ff ff ff  ff ff 00 00  ff ff 40 eb  0c 20 0f 52
    10 d8 00 00  36 02 a6 00  82 ea 14 c2  e9 63 76 33
    7a 75 7a 75  f7 a2 d5 5c  19 f7 4d ff  e9 30 f8 80
    ];
jedec-id = [ef 40 16];

I tried it with this updated DTS but still no luck when trying to write using QSPI. 

&qspi {
    status = "okay";
    pinctrl-0 = <&qspi_default>;
    pinctrl-1 = <&qspi_sleep>;
    pinctrl-names = "default", "sleep";
    w25q32: w25q32jv@0 {
        compatible = "nordic,qspi-nor";
        reg = <0>;
        writeoc = "pp4io";    // Quad Input Page Program
        readoc = "read4io";   // Fast Read Quad I/O
        sck-frequency = <8000000>; // 8MHz SPI clock
        jedec-id = [EF 40 16];  // Manufacturer and device ID
        size = <33554432>;  // 4MB (32Mb)
        sfdp-bfp = [
            e5 20 f9 ff  ff ff ff 01  44 eb 08 6b  08 3b 42 bb
            fe ff ff ff  ff ff 00 00  ff ff 40 eb  0c 20 0f 52
            10 d8 00 00  36 02 a6 00  82 ea 14 c2  e9 63 76 33
            7a 75 7a 75  f7 a2 d5 5c  19 f7 4d ff  e9 30 f8 80
        ];
        has-dpd;
        t-enter-dpd = <10000>;  // Enter Deep Power Down time (10µs)
        t-exit-dpd = <35000>;   // Exit Deep Power Down time (35µs)
        quad-enable-requirements = "S2B1v1";  // QE bit in Status Register 2, bit 1
    };
};

Perhaps it is hardware related? I was reading that for QSPI I need to length match traces. I did not do this on my current board as I was originally designing only for SPI usage. Would running at 8MHz be slow enough though to compensate for length mismatch if that was the issue?

Anyways thanks for pointing out using this sample to read the information. I will move on with my project using SPI instead as that works. 

[Sigurd Hellesvik]

Doug K said:

Anyways thanks for pointing out using this sample to read the information. I will move on with my project using SPI instead as that works. 

I think this is a wise next step.

I have seen other tickets where the QSPI driver can needs some configuring with other external flash chips, so we can look into that later if you want.

However, using SPI will give us more information if we want to debug more, or it can serve as a solution, and we don't have to look more at why QSPI don't work for you. Up to you

[Doug K]

I have two other boards with NRF54L15's paired with the same W23Q32 flash. I will retest on those to see if different boards have different results. Also I am not sure if its related but I didn't realize I was using the NFC GPIO's when designing the board. I am not sure if those IO's have any limitations compared to other GPIO's. I did have to use the config CONFIG_NFCT_PINS_AS_GPIOS=y to make those work.

I do have one more question, what's the best way to read/write the status bits in SPI? I want to read/write whether the chip is in QSPI mode or not.

[Sigurd Hellesvik]

Doug K said:

I do have one more question, what's the best way to read/write the status bits in SPI? I want to read/write whether the chip is in QSPI mode or not.

I do not understand the question fully. Do you mean how to read the ENABLE register?

[Doug K]

I believe I answered my own question and didn't update. 

I was talking about the Quad Enable bit for the flash. There is a bit in the status register that is supposed to be written depending on if you want to be in QSPI mode or not. I believe this is what the nordic qpsi param "quad-enable-requirements" means. It tells the software where the QE bit is located. 

quad-enable-requirements = "S2B1v1";

I found out that none of this is relevant though, as I ordered the flash chip that has the QE bit fixed to ON. :)