PPI registers on nrf52832

[Paul]

Hi,

I was wondering if anyone could clarify why there are enable, set and clear (CHEN, CHENSET, CHENCLR) for the PPI channels when according to the data sheet they all appear to do the same thing?

Do the registers need to be used in combination or a particular sequence and do they still need to be enabled / set if a channel group is used?

[RK]

For the same reason there are xxx, xxxSET and xxxCLR channels for just about every other peripheral. The xxx updates the state of every single bit either to set or clear, the xxxSET channel enables you to set bits you set to '1' without changing any other bits and the xxxCLR channel lets you clear bits which are '1' in the value you set without changing any other bits.

Without those SET and CLR channels you'd have to read the word, mask out anything you want to clear, mask in anything you want to set, and then write it back. Having the SET and CLR registers allows you to do that two-part operation in one write.

[Paul]

Thanks, that makes sense.
So should the CHEN register always reflect the current state regardless of how the channel is enabled disabled? For example if a channel is part of a group, and that group is enabled - should the CHEN register location for that channel show as 1?

[RK]

Believe so - why don't you just test it - 2 minutes.

[Paul]

Just in case anyone else comes across this - Yes the CHEN register does reflect changes made by enabling / disabling groups.