Is watch dog running while flash page erase?

[braucadr]

Hi,

When a watch dog timeout occurs, I want to save some data to the flash memory prior to reset (namely the RTC count value). Therefore I enabled the wdt interrupt. The manual says that I have two 32.768 kHz clock cycles to do my tasks in the ISR before the watch dog reset is issued. The problem is that I have to erase a page before writing my data to the flash and this takes maximum 22.3ms according to the spec.

So my question is whether this two cycles keep counting during erase when I set CONFIG.HALT = 0. I think they shouldn't as CPU is halted during erase and the wdt is paused while cpu is halted.

Thanks for your help

[Einar Thorsrud]

It is not possible to delay the watchdog from resetting the chip in this case. The watchdog is designed to make it impossible for it to be disabled by a mistake. For example, a fault could accidentally try to disable the watchdog, and this should not be possible. Therefor the watchdog’s configuration registers will be blocked for further configuration after it is started, and once a timeout has occurred, the impending watchdog reset will always be effectuated. This behavior is the same for both nRF51 and nRF52.

Refer to the Watchdog timer chapter in the spec for details.

[braucadr]

Hi Einar, thanks for your answer. I agree, it should not be possible to disable the watchdog by accident. It would be nice though to have a little more time in the watchdog ISR to save some crucial data. Particularly as the RTC.COUNTER register is reset during watchdog reset.