UART DMA confusion

[silvio3105]

Hi,

I'm working with UART with DMA(UARTE) on nRF52840. UART does not have HW flow control, just RX-TX.

I'm confused with DMA part. Is DMA circular or I have to reset it back to 0? How I can get DMA byte index?

Until now I used DMA in circular mode and periodically transfer data from DMA buffer to buffer for processing. DMA byte index is needed but I'm not sure can I get it.

For now, only way to make design like this is to use classic UART and emulate DMA with enabled interrupts.

I use nRF5 SDK.

[Turbo J]

Why do yo care? The NRF connect SDK ships with ready-to-use UART drivers.

HW flow control is strongly recommended once baud rate exceeds roughly 9600 baud due to how BTLE works (it can block the CPU for a while).

[silvio3105]

I care because I don't want and like to use something without knowing how it works. I use nrfx hal. I forgot to say I use nRF5 SDK.
This is not about SDK, it's about how UARTE works on HW level.

[hmolesworth]

There isn't a register which allows reading of the current DMA data pointer, but there is an implicit event which can be used to trigger a counter for bytes actually sent. It's a bit clumsy, as the DMA is really designed for discreet packets of data, such packets can be variable length but are expected to be sent individually, though packet n+1 can be started before packet n completes as the Tx ptr is double-buffered. Using discrete packets and checking TXD.AMOUNT (Number of bytes transferred in the last transaction) allows manipulating a circular buffer, but unless the packets exactly align with the end of the circular buffer the next packet would be started at the beginning of the buffer and not at the end of the previous packet in the buffer. Ideally all packets are size N bytes and then the buffer can be some integer * N in size and an index of packets allows simple update of TXD.PTR.

"After each byte has been sent over the TXD line, a TXDRDY event will be generated"

[silvio3105]

Damn. Yes, I can count RX bytes via RXDRDY event but without HW flow control SD can cause counter to skip and desync counter with actual buffer.
Communication is with GSM modem. With all URCs, this DMA design is really bad.

[hmolesworth]

It's pretty limited. An alternative, should you have control over both ends of the link, is to switch to SPIM. Hardware flow control via an input pin can be implemented using TASKS_SUSPEND and TASKS_RESUME coupled via PPI to the rising and falling edge of the input pin. I wrote an example using 2 x PPI at the end of the post how-to-do-spim-with-handshakes based on Susheel's toggle suggestion