While collecting 2-byte samples via SPI4 (with a 32 MHz clock) using PPI and timers—one triggering transfers at 400 kHz and another handling an interrupt every 512 samples (counter mode incrementing every SPI transfer end via PPI) to switch the SPI DMA buffer address—erroneous samples occur at buffer boundaries (mostly single, but sometimes multiple). Four buffers of 512 samples each are used.
It appears that either writing samples or switching buffers is not keeping up. However, the time between the 512-sample timer interrupt and the buffer address switch is shorter than the time until the next SPI transfer is triggered.
The program runs with Zephyr and BLE on net core. The sampling timer priority is set to 1, SPI and timer for switching buffers are set to 0 priority. Could Zephyr or other processor interrupts preempt the acquisition process to such an extent? Or is the issue elsewhere?
