FLPR/VPR documentation on VIO, VTIM, etc

[bharrisau]

Trying to work through using the FLPR for a virtual peripheral. I can infer things like the VTIM sets counter 0 and 1 to automatically buffer data in/out via the VIO setup. But it would be a bit easier to understand with an overview of the VPR/FLPR peripherals.

Is this available?

[Sigurd Hellesvik]

Hi,

For the FLPR Software Defined Peripherals (SDP), we got some samples over at https://github.com/nrfconnect/sdk-nrf/tree/main/applications/sdp, one of which even got a bit of documentation.

For the Datasheet we got VPR — RISC-V CPU.

Or you could always dig in some source files: https://github.com/zephyrproject-rtos/hal_nordic/blob/master/nrfx/mdk/nrf54l15_flpr_peripherals.h

Are these what you look for?

Regards,
Sigurd Hellesvik

[bharrisau]

I was hoping to clarify a few of the details. For example:

• Maximum VIO buffered size - seems like 32 bits, but mSPI works in 8 bit units only. Why not more?
• Are OUTB/INB double buffered? i.e. if I call `nrf_vpr_csr_vio_out_buffered_reversed_byte_set`, does the first call load the OUTB shift register, the second call buffer, and the third call stall the CPU until the first buffer is shifted out?
• How does reading `nrf_vpr_csr_vio_in_buffered_reversed_byte_get` work? Does it stall the CPU until a full frame is available (i.e. shift_count * frame_width bits?). Is the shift register still reading in data while there is an INB waiting to be read?
• VTIM Counter 0 can trigger off "VIO Event", what are VIO events?
• Can I use VIO input to stall the CPU waiting for a rising edge? Or is the quickest option to do a read and conditional jump?
• What does enabling Real Time Peripheral do, and when would I need to do it? 
• Can I set interrupts on OUTB empty or INB full?
• Is there any options for handling fractional VTIM counters, other than manually updating TOP value each iteration. e.g. for 25Mhz - top needs to be 4.12 - so swapping between 4 and 5.

I wasn't able to find details on things like that. Could only guess based on the GPIO and mSPI examples.

Edit: Had a quick think on the 25MHz from what is available. Actualy needs CNT1_TOP to alternate between 1 and 2 as it operates on half-cycles. So maybe set CNT1_TOP to 1 and call CNT1_ADD+1 every 5 cpu cycles - can't really use the CPU for anything else though. Maybe use the CNT0_IRQ to trigger once a full cycle and call the CNT1_ADD in that way.

[Sigurd Hellesvik]

I get what you mean yes. I will see which of the questions I can find answers for soon.

But first, could I ask: what is the use-case you have here?

(Let me know if you rather want the ticket to be private for that)

[bharrisau]

No worries. I was looking at setting up ethernet MAC running 10Mbps via either RMII or RGMII. I think RMII will be fine, and I'll just ignore the 50MHz clock signal from the PHY (signals are repeated for 10 clocks - effectively 5Mhz) and only need 6 IO to the RTP. RGMII would be more technically correct, as I'd be able to correctly clock data against a 2.5Mhz clock but it needs 12 IO.

[Sigurd Hellesvik]

Here is what I found:

The information you are asking about is not yet publicly available, and I can not share it here.

If you want to push the questions a bit, you can try to Contact your local Nordic Semiconductor sales representative, and perhaps they can help you.