1.Official development board with MX25R6435F, showing normal Matter project startup logs.
[00:00:00.531,831] spi_nor: mx25r6435f@0: 8 MiBy flash
[00:00:00.534,013] mcuboot: Starting bootloader
[00:00:00.534,543] mcuboot: Primary image: magic=unset, swap_type=0x1, copy_done=0x3, image_ok=0x3
[00:00:00.534,668] mcuboot: Secondary image: magic=unset, swap_type=0x1, copy_done=0x3, image_ok=0x3
[00:00:00.534,673] mcuboot: Boot source: none
[00:00:00.534,843] mcuboot: Image index: 0, Swap type: none
mrs:~$ *** Booting My Application v9.1.0-868d3758095a ***
*** Using nRF Connect SDK v2.9.0-7787b2649840 ***
*** Using Zephyr OS v3.7.99-1f8f3dc29142 ***
2.Private hardware with GD25WQ32E, startup logs of the same Matter project:
00:00:10.256,250] <inf> spi_nor: GD25WQ32E@0: 4 MiBy flash
[00:00:10.256,264] <inf> mcuboot: Starting bootloader
[00:00:10.256,795] <inf> mcuboot: Primary image: magic=unset, swap_type=0x1, copy_done=0x3, image_ok=0x3
[00:00:10.256,921] <inf> mcuboot: Secondary image: magic=unset, swap_type=0x1, copy_done=0x3, image_ok=0x3
[00:00:10.256,926] <inf> mcuboot: Boot source: none
[00:00:10.257,098] <inf> mcuboot: Image index: 0, Swap type: none
3.The modifications for adapting to the GD25WQ32E are as follows:
3.1 nrf54l_05_10_15_cpuapp_common.dtsi
&spi00 {
status = "okay";
cs-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&spi00_default>;
pinctrl-1 = <&spi00_sleep>;
pinctrl-names = "default", "sleep";
gd25wq32: GD25WQ32E@0 {
compatible = "jedec,spi-nor";
status = "okay";
reg = <0>;
spi-max-frequency = <32000000>;
jedec-id = [c8 65 16];
sfdp-bfp = [
e5 20 f1 ff ff ff ff 01 44 eb 08 6b 08 3b 42 bb
ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52
10 d8 00 ff 63 92 fd fe 83 2f 26 46 ec 82 18 44
7a 75 7a 75 04 bd d5 5c 00 06 64 00 08 10 00 00
];
size = <33554432>;
has-dpd;
t-enter-dpd = <10000>;
t-exit-dpd = <35000>;
};
};
3.2 pm_static_nrf54l15dk_nrf54l15_cpuapp.yml
external_flash (0x400000 - 4096kB):
+--------------------------------------------------+
+---0x0: mcuboot_secondary (0x164000 - 1424kB)-----+
| 0x0: mcuboot_secondary_pad (0x800 - 2kB) |
| 0x800: mcuboot_secondary_app (0x163800 - 1422kB) |
+--------------------------------------------------+
| 0x164000: external_flash (0x29c000 - 2672kB) |
+--------------------------------------------------+
flash_primary (0x17d000 - 1524kB):
+---------------------------------------------------+
| 0x0: mcuboot (0xd000 - 52kB) |
+---0xd000: mcuboot_primary (0x164000 - 1424kB)-----+
| 0xd000: mcuboot_pad (0x800 - 2kB) |
+---0xd800: mcuboot_primary_app (0x163800 - 1422kB)-+
| 0xd800: app (0x163800 - 1422kB) |
+---------------------------------------------------+
| 0x171000: factory_data (0x2000 - 8kB) |
| 0x173000: settings_storage (0xa000 - 40kB) |
+---------------------------------------------------+
otp (0x4fc - 1kB):
+-----------------------------+
| 0xffd500: otp (0x4fc - 1kB) |
+-----------------------------+
sram_primary (0x40000 - 256kB):
+--------------------------------------------+
| 0x20000000: sram_primary (0x40000 - 256kB) |
+--------------------------------------------+
3.3 sysbuild/mcuboot/boards/nrf54l15dk_nrf54l15_cpuapp.conf
CONFIG_BOOT_MAX_IMG_SECTORS=512
CONFIG_SPI_NOR_FLASH_LAYOUT_PAGE_SIZE=4096
4. SFDP info
*** Booting nRF Connect SDK v2.9.0-7787b2649840 ***
*** Using Zephyr OS v3.7.99-1f8f3dc29142 ***
mx25r6435f@0: SFDP v 1.6 AP ff with 3 PH
PH0: ff00 rev 1.6: 16 DW @ 30
Summary of BFP content:
DTR Clocking not supported
Addressing: 3-Byte only
4-KiBy erase: uniform
Support QSPI XIP
Support 1-1-1
Support 1-1-2: instr 3Bh, 0 mode clocks, 8 waits
Support 1-1-4: instr 6Bh, 0 mode clocks, 8 waits
Support 1-2-2: instr BBh, 0 mode clocks, 4 waits
Support 1-4-4: instr EBh, 2 mode clocks, 4 waits
Flash density: 8388608 bytes
ET1: instr 20h for 4096 By; typ 48 ms, max 384 ms
ET2: instr 52h for 32768 By; typ 240 ms, max 1920 ms
ET3: instr D8h for 65536 By; typ 480 ms, max 3840 ms
Chip erase: typ 52000 ms, max 312000 ms
Byte program: type 32 + 1 * B us, max 192 + 6 * B us
Page program: typ 896 us, max 5376 us
Page program size: 256 By
Suspend: B0h ; Resume: 30h
DPD: Enter B9h, exit ABh ; delay 40000 ns ; poll 0x3d
HOLD or RESET Disable: unsupported
QER: 2
0-4-4 Mode methods: entry 0x9 ; exit 0x2f
4-4-4 Mode sequences: enable 0x00 ; disable 0x0
Soft Reset and Rescue Sequence support: 0x10
Status Register 1 support: 0x70
size = <67108864> bits;
sfdp-bfp = [
e5 20 f1 ff ff ff ff 03 44 eb 08 6b 08 3b 04 bb
ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52
10 d8 00 ff 23 72 f5 00 82 ed 04 cc 44 83 48 44
30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff
];
PH1: ffc2 rev 1.0: 4 DW @ 110
sfdp-ffc2 = [
00 36 50 16 9d f9 c0 64 fe cf ff ff ff ff ff ff
];
PH2: ff84 rev 1.0: 2 DW @ c0
sfdp-ff84 = [
00 00 f0 ff ff ff ff ff
];
jedec-id = [c2 28 17];
*** Booting nRF Connect SDK v2.9.0-7787b2649840 ***
*** Using Zephyr OS v3.7.99-1f8f3dc29142 ***
mx25r6435f@0: SFDP v 1.6 AP ff with 2 PH
PH0: ff00 rev 1.6: 16 DW @ 30
Summary of BFP content:
DTR Clocking not supported
Addressing: 3-Byte only
4-KiBy erase: uniform
Support QSPI XIP
Support 1-1-1
Support 1-1-2: instr 3Bh, 0 mode clocks, 8 waits
Support 1-1-4: instr 6Bh, 0 mode clocks, 8 waits
Support 1-2-2: instr BBh, 2 mode clocks, 2 waits
Support 1-4-4: instr EBh, 2 mode clocks, 4 waits
Flash density: 4194304 bytes
ET1: instr 20h for 4096 By; typ 112 ms, max 896 ms
ET2: instr 52h for 32768 By; typ 304 ms, max 2432 ms
ET3: instr D8h for 65536 By; typ 512 ms, max 4096 ms
Chip erase: typ 28000 ms, max 224000 ms
Byte program: type 72 + 5 * B us, max 576 + 40 * B us
Page program: typ 1024 us, max 8192 us
Page program size: 256 By
Suspend: 75h ; Resume: 7Ah
DPD: Enter B9h, exit ABh ; delay 30000 ns ; poll 0x01
HOLD or RESET Disable: unsupported
QER: 6
0-4-4 Mode methods: entry 0x4 ; exit 0x01
4-4-4 Mode sequences: enable 0x00 ; disable 0x0
Soft Reset and Rescue Sequence support: 0x10
Status Register 1 support: 0x08
size = bits;
sfdp-bfp = [
e5 20 f1 ff ff ff ff 01 44 eb 08 6b 08 3b 42 bb
ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52
10 d8 00 ff 63 92 fd fe 83 2f 26 46 ec 82 18 44
7a 75 7a 75 04 bd d5 5c 00 06 64 00 08 10 00 00
];
PH1: ffc8 rev 1.0: 3 DW @ 90
sfdp-ffc8 = [
00 36 50 16 9e f9 77 64 fc cb ff ff
];
jedec-id = [c8 65 16];
It seems that the boot has already recognized the GD25WQ32E, but what additional settings are needed to ensure the correct jump?
