COMP (or PPI) drops event

[snoopy20]

Hi,

I previously wrote about an unexpected behaviour which I've made a diagram for below. It's relatively simple though, the COMP watches a voltage and fires a toggle event through PPI which is received by GPIOTE which toggles it's pin which controls an external circuit responsible for the voltage that COMP watches.

First the external circuit is switched off by a secondary means and the system is synced, so GPIOTE goes high and COMP goes high, then the secondary means is turned off so the driver activates and then it's purely a hardware based implementation.

I previously replicated the behaviour when the COMP speed was set to normal. This suggested that PPI or GPIOTE couldn't keep up with the events it was generating OR COMP was/is sometimes failing to generate the toggle event when the voltage has recovered. The behaviour means the GPIOTE remains low when the voltage has recovered.

The COMP speed was set to low, so 1MHz, and on the bench this appeared to have resolved the issue. However, a user is now reporting it again.

[Susheel Nuguru]

The main issue here seems to be that your loop here seems very fragile where it depends on toggling instead of relying on a deterministic state.

My suggestion is that you can map

COMP->EVENT_UP → GPIOTE TASKS_SET
COMP->EVENT_DOWN → GPIOTE TASKS_CLR

So that we are sure that the ping goes high if the voltage goes above threshold and vice versa.

[snoopy20]

I don't see why it's fragile, only the COMP generates the signal and only COMP has control over the 'thing' that affects the signal. It's closer to a true hardware UVLO implementation this way.

Originally many moons ago I had implemented it by the method you describe but found it didn't work, probably because the comp was generating the events too close together and they were racing to be processed. This may however have been with the COMP on normal or fast speed and may be worth a revisit, but I have my doubts whether it will fix the underlying issue.

I should elaborate further. The external circuit is a slow turn-on (ramps) but a fast off. This will mean when the COMP generates its below signal triggering gpiote the above signal is going to follow quickly. Indeed it is this above signal which is 'missing' on occasion. 

I know that setting the COMP to slow almost fixes the issue.

[snoopy20]

The frequency of the loop is dictated by the speed of the COMP, which in low power mode is 1MHz according to the datasheet.

Your understanding of the system is correct. Then your third points are:

1. correct, if the sink is too much VDD will drop
2. the speed of the missing event (Vdd recovered) is dependent on how fast TLV62090 turns off and then how fast COMP toggles its state. The turn off by TLV62090 will be very fast, microseconds at worst. The state (Vdd recovered) is then waiting for COMP to detect it.
3. there's really not much to it. COMP detects Vdd, state goes to PPI/GPIOTE and toggles thing which affects Vdd, so equilibrium.

The PPI GRP workaround is a success (the RTC is just to clock, could use anything). I've ran it for hours.

The solutions slows down the EVENT_UP propagation and so clearly tells me the problem is not with COMP or PPI because it's now working, so the problem is with GPIOTE. It isn't fast enough to handle 1MHz PPI events.

  // GPIOTE turn-offs
  NRF_PPI->CH[CFG_PPI_POWERMANAGER_UVLO_FRONTREAR].EEP = (uint32_t) &NRF_COMP->EVENTS_DOWN;
  NRF_PPI->CH[CFG_PPI_POWERMANAGER_UVLO_FRONTREAR].TEP = (uint32_t) &NRF_GPIOTE->TASKS_CLR[CFG_GPIOTE_POWERMANAGER_FRONT];
  NRF_PPI->FORK[CFG_PPI_POWERMANAGER_UVLO_FRONTREAR].TEP = (uint32_t) &NRF_GPIOTE->TASKS_CLR[CFG_GPIOTE_POWERMANAGER_REAR];

  // -- enables first group, awaits a tick
  NRF_PPI->CH[CFG_PPI_POWERMANAGER_UVLO_GROUP].EEP = (uint32_t) &NRF_COMP->EVENTS_UP;
  NRF_PPI->CH[CFG_PPI_POWERMANAGER_UVLO_GROUP].TEP = (uint32_t) &NRF_PPI->TASKS_CHG[CFG_PPI_GROUP_POWERMANAGER_ENABLE_NEXT].EN;

  // -- enables next group on tick, disables self (one shot)
  NRF_PPI->CH[CFG_PPI_POWERMANAGER_TIMER_GROUP_NEXT].EEP = (uint32_t) &CFG_SCHEDULER_TIMER->EVENTS_TICK;
  NRF_PPI->CH[CFG_PPI_POWERMANAGER_TIMER_GROUP_NEXT].TEP = (uint32_t) &NRF_PPI->TASKS_CHG[CFG_PPI_GROUP_POWERMANAGER_ENABLE_NEXT].DIS;
  NRF_PPI->FORK[CFG_PPI_POWERMANAGER_TIMER_GROUP_NEXT].TEP = (uint32_t) &NRF_PPI->TASKS_CHG[CFG_PPI_GROUP_POWERMANAGER_ENABLE_SET].EN;
  NRF_PPI->CHG[CFG_PPI_GROUP_POWERMANAGER_ENABLE_NEXT] = 1 << CFG_PPI_POWERMANAGER_TIMER_GROUP_NEXT;

  // -- sets outputs, disables self (one shot)
  NRF_PPI->CH[CFG_PPI_POWERMANAGER_TIMER_FRONTREAR].EEP = (uint32_t) &CFG_SCHEDULER_TIMER->EVENTS_TICK;
  NRF_PPI->CH[CFG_PPI_POWERMANAGER_TIMER_FRONTREAR].TEP = (uint32_t) &NRF_GPIOTE->TASKS_SET[CFG_GPIOTE_POWERMANAGER_FRONT];
  NRF_PPI->FORK[CFG_PPI_POWERMANAGER_TIMER_FRONTREAR].TEP = (uint32_t) &NRF_GPIOTE->TASKS_SET[CFG_GPIOTE_POWERMANAGER_REAR];
  NRF_PPI->CH[CFG_PPI_POWERMANAGER_TIMER_GROUP_SET].EEP = (uint32_t) &CFG_SCHEDULER_TIMER->EVENTS_TICK;
  NRF_PPI->CH[CFG_PPI_POWERMANAGER_TIMER_GROUP_SET].TEP = (uint32_t) &NRF_PPI->TASKS_CHG[CFG_PPI_GROUP_POWERMANAGER_ENABLE_SET].DIS;
  NRF_PPI->CHG[CFG_PPI_GROUP_POWERMANAGER_ENABLE_SET] = 1 << CFG_PPI_POWERMANAGER_TIMER_FRONTREAR | 1 << CFG_PPI_POWERMANAGER_TIMER_GROUP_SET;

I hope you like the solution, I'm pretty pleased with myself. With NRF52 there's always a way.

[Hieu]

I am afraid I am unqualified to comment on this solution . I see what you are doing, but I lack the knowledge to evaluate it.

But it's great to know that you have a working solution now.

I will follow-up regarding the unanswered questions once I receive a response for my internal query. However, it looks like that has to be after the Easter holiday. My apology for the inconvenience.

[snoopy20]

Sure, there's no rush, the 'solution' is working and everyone is happy.

[Hieu]

Hi snoopy20,

I am updating regarding one of the questions:

snoopy20 said:

2. The upper hysteresis resistor is set to trigger at 4.8v (nominal voltage is 5v +/- 1%). The tolerance of the comp hysteresis is unknown, does it change with temperature, does the comp speed change the tolerance (it does on PIC16 as an example)?

Both can contribute the tolerance of COMP. Temperature makes the reference voltage drift, and higher operation speed could potentially have an impact on internal offset of COMP, limiting accuracy of the circuit.

The other questions will have to wait even longer unless they become critical for the design. Our apologies for the inconvenience.

[snoopy20]

No problem, the current solution is working in all temperatures so it is known to not be the problem. It is known that GPIOTE can't keep up with the 1MHz speed of PPI.

It's easy to wire something up on NRF52DK by connecting a digital pin to a capacitor with pull-up enabled in parallel with an analog pin for the comp and validating the issue. I figure the newer chips are using the same GPIOTE so worth the investigation?

[Hieu]

snoopy20 said:

I figure the newer chips are using the same GPIOTE so worth the investigation?

I really don't know, and even if I do, I doubt I have the liberty to comment about it on DevZone. But I will trust our engineers' judgement on this.