Flashing a custom nRF5340 board using a Segger J-Link Plus Compact

[lcj]

I am trying to flash a new board using a Segger J-Link Plus Compact. I use the same code to flash my nRF5340DK and it runs fine. I see the debug statements in the JLinkRTTViewer: I have a board definition which is building and can flash the board:

Flashing build_4 to 000000000
west flash -d /Users/zzzzzz/Projects/GitHub/yyyyy/hello_world_sysbuild/build_4 --dev-id 000000000

-- west flash: rebuilding
[0/10] Performing build step for 'hello_world_sysbuild'
ninja: no work to do.
[1/10] Performing build step for 'mcuboot'
ninja: no work to do.
[4/10] cd /Users/zzzzz/Projects/GitHub/yyyyy/hello_world_sysbuild/build_4/_sysbuild && /opt/nordic/ncs/toolchains/b8efef2ad5/Cellar/cmake/3.21.0/bin/cmake -E true
[6/9] No install step for 'mcuboot'
[7/9] Completed 'mcuboot'
[8/9] cd /Users/zzzzz/Projects/GitHub/yyyyy/hello_world_sysbuild/build_4/_sysbuild && /opt/nordic/ncs/toolchains/b8efef2ad5/Cellar/cmake/3.21.0/bin/cmake -E true
-- west flash: using runner nrfjprog
-- runners.nrfjprog: reset after flashing requested
-- runners.nrfjprog: Flashing file: /Users/zzzzz/Projects/GitHub/yyyyy/hello_world_sysbuild/build_4/merged.hex
[ #################### ]   5.137s | Erase file - Done erasing                                                          
[ #################### ]   1.050s | Program file - Done programming                                                    
[ #################### ]   1.011s | Verify file - Done verifying                                                       
Applying pin reset.
-- runners.nrfjprog: Board with serial number 000000000 flashed successfully.

I have set the board using the jlinkexe:

SEGGER J-Link Commander V8.12a (Compiled Jan  9 2025 14:39:08)
DLL version V8.12a, compiled Jan  9 2025 14:38:28

Connecting to J-Link via USB...O.K.
Firmware: J-Link V11 compiled Dec  4 2024 17:53:35
Hardware version: V11.00
J-Link uptime (since boot): 0d 00h 00m 53s
S/N: 000000000
License(s): RDI, FlashBP, FlashDL, JFlash, GDB
USB speed mode: High speed (480 MBit/s)
VTref=3.300V (fixed)


J-Link>Power On
J-Link>ShowHWStatus
VTref=3.300V (fixed)
ITarget=6mA
TCK=0 TDI=0 TDO=0 TMS=0 TRES=1 TRST=0
Supported target interface speeds:
 - 180 MHz/n, (n>=12). => 15000kHz, 13846kHz, 12857kHz, ...
 - Adaptive clocking
J-Link>ShowHWStatus
VTref=0.000V
TCK=0 TDI=0 TDO=0 TMS=0 TRES=0 TRST=0
Supported target interface speeds:
 - 16 MHz/n, (n>=4). => 4000kHz, 3200kHz, 2666kHz, ...
 J-Link>

I also don't see the device in the nRF Connect iOS app like I do with the nRF5340DK. I'm not sure how I debug this?

[Håkon Alseth]

Hi,

 

It looks like you are connecting with JTAG instead of SWD.

Try issuing "si 1" first, then a "connect".

And please note that you should flash both cores in the case of the nRF5340. nrfjprog can do this for you, by flashing the "merged.hex" file in your build folder.

 

Kind regards,

Håkon

[lcj]

I added added SB_CONFIG_NETCORE_HCI_IPC=y to the sysbuild.conf and got:

Flashing build_4 to 000000000
west flash -d /Users/zzzzz/Projects/GitHub/yyyyy/hello_world_sysbuild/build_4 --dev-id 000000000

-- west flash: rebuilding
[0/15] Performing build step for 'hci_ipc'
ninja: no work to do.
[1/15] Performing build step for 'hello_world_sysbuild'
ninja: no work to do.
[4/15] cd /Users/zzzzz/Projects/GitHub/yyyyy/hello_world_sysbuild/build_4/_sysbuild && /opt/nordic/ncs/toolchains/b8efef2ad5/Cellar/cmake/3.21.0/bin/cmake -E true
[5/14] Performing build step for 'mcuboot'
ninja: no work to do.
[8/14] cd /Users/zzzzz/Projects/GitHub/yyyyy/hello_world_sysbuild/build_4/_sysbuild && /opt/nordic/ncs/toolchains/b8efef2ad5/Cellar/cmake/3.21.0/bin/cmake -E true
[10/13] No install step for 'mcuboot'
[11/13] Completed 'mcuboot'
[12/13] cd /Users/zzzzz/Projects/GitHub/yyyyy/hello_world_sysbuild/build_4/_sysbuild && /opt/nordic/ncs/toolchains/b8efef2ad5/Cellar/cmake/3.21.0/bin/cmake -E true
WARNING: Specifying runner options for multiple domains is experimental.
If problems are experienced, please specify a single domain using '--domain <domain>'
-- west flash: using runner nrfjprog
-- runners.nrfjprog: reset after flashing requested
-- runners.nrfjprog: Flashing file: /Users/zzzzz/Projects/GitHub/yyyyy/hello_world_sysbuild/build_4/merged_CPUNET.hex
[ #################### ]   8.256s | Erase file - Done erasing                                                          
[ #################### ]   0.971s | Program file - Done programming                                                    
[ #################### ]   0.973s | Verify file - Done verifying                                                       
Applying pin reset.
-- runners.nrfjprog: Board with serial number 000000000 flashed successfully.
-- west flash: using runner nrfjprog
-- runners.nrfjprog: reset after flashing requested
-- runners.nrfjprog: Flashing file: /Users/zzzzz/Projects/GitHub/yyyyy/hello_world_sysbuild/build_4/merged.hex
[ #################### ]   4.922s | Erase file - Done erasing                                                          
[ #################### ]   1.057s | Program file - Done programming                                                    
[ #################### ]   1.013s | Verify file - Done verifying                                                       
Applying pin reset.
-- runners.nrfjprog: Board with serial number 000000000 flashed successfully.

which looks like I'm flashing the CPUNET as well, correct?

I went into jlink commander and set SelectInterface SWD

Type "connect" to establish a target connection, '?' for help
J-Link>SelectInterface SWD
Selecting SWD as current target interface.
J-Link>

And flashed and connected with the jlinkrttviewer again:

LOG: J-Link RTT Viewer V8.12a: Logging started.
LOG: Terminal 0 added.
LOG: Connecting to J-Link via USB...
LOG: Device "NRF5340_XXAA_APP" selected.
LOG: ConfigTargetSettings() start
LOG: ConfigTargetSettings() end - Took 4us
LOG: InitTarget() start
LOG: InitTarget() end - Took 1.93ms
LOG: Found SW-DP with ID 0xZZZZZZZZ
LOG: DPIDR: 0x6BA02477
LOG: CoreSight SoC-400 or earlier
LOG: AP map detection skipped. Manually configured AP map found.
LOG: AP[0]: AHB-AP (IDR: Not set, ADDR: 0x00000000)
LOG: AP[1]: AHB-AP (IDR: Not set, ADDR: 0x00000000)
LOG: AP[2]: MEM-AP (IDR: Not set, ADDR: 0x00000000)
LOG: AP[3]: MEM-AP (IDR: Not set, ADDR: 0x00000000)
LOG: AP[0]: Core found
LOG: AP[0]: AHB-AP ROM base: 0xE00FE000
LOG: CPUID register: 0x410FD214. Implementer code: 0x41 (ARM)
LOG: Feature set: Mainline
LOG: Cache: No cache
LOG: Found Cortex-M33 r0p4, Little endian.
LOG: FPUnit: 8 code (BP) slots and 0 literal slots
LOG: Security extension: implemented
LOG: Secure debug: enabled
LOG: CoreSight components:
LOG: ROMTbl[0] @ E00FE000
LOG: [0][0]: E00FF000 CID B105100D PID 000BB4C9 ROM Table
LOG: ROMTbl[1] @ E00FF000
LOG: [1][0]: E000E000 CID B105900D PID 000BBD21 DEVARCH 47702A04 DEVTYPE 00 Cortex-M33
LOG: [1][1]: E0001000 CID B105900D PID 000BBD21 DEVARCH 47701A02 DEVTYPE 00 DWT
LOG: [1][2]: E0002000 CID B105900D PID 000BBD21 DEVARCH 47701A03 DEVTYPE 00 FPB
LOG: [1][3]: E0000000 CID B105900D PID 000BBD21 DEVARCH 47701A01 DEVTYPE 43 ITM
LOG: [1][5]: E0041000 CID B105900D PID 002BBD21 DEVARCH 47724A13 DEVTYPE 13 ETM
LOG: [1][6]: E0042000 CID B105900D PID 000BBD21 DEVARCH 47701A14 DEVTYPE 14 CSS600-CTI
LOG: [0][1]: E0040000 CID B105900D PID 000BBD21 DEVARCH 00000000 DEVTYPE 11 TPIU
LOG: RTT Viewer connected.

Still nothing printing to the terminal and no BLE advertising. Did I do what you said correctly?

Actually, when connecting I selected SWD;

[Håkon Alseth]

Hi,

 

Sorry, I might have misunderstood the initial issue. Is the issue that your custom board does not run as expected?

 

Does your design have DCDC inductors in place?

If not, please add this to your overlay:

&vregmain {
	regulator-initial-mode = <NRF5X_REG_MODE_LDO>;
};

&vregradio {
	regulator-initial-mode = <NRF5X_REG_MODE_LDO>;
};

 

Does your design have a external 32k src? if not, you should enable internal 32k rc oscillator by adding this to your prj.conf:

CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y

 

Kind regards,

Håkon

[lcj]

Q: Does your design have DCDC inductors in place?
A: Yes, I used DCC mode for nRF chip and inductors are from datasheet (you can see it with designators L3,L4,L5,L6,L7 in schematic design), and capacitors are on the PCB too (C17..C46).

Q: Does your design have a external 32k src?
A: Yes, we have 32MHz X1 crystal and 32.768kHz X2 crystal (both with correctly calculated capacitors C43..C46).

Testing again. It seems to flash:

 *  Executing task: nRF Connect: Flash: blinky_custom_board/blinky_custom_board (active) 

Flashing blinky_custom_board to *********
west flash -d /Users/*****/Projects/GitHub/*****/blinky_custom_board/*****_build --domain blinky_custom_board --dev-id 851007258

-- west flash: rebuilding
[0/5] Performing build step for 'blinky_custom_board'
ninja: no work to do.
[2/5] No install step for 'blinky_custom_board'
[3/5] Completed 'blinky_custom_board'
[4/5] cd /Users/*****/Projects/GitHub/*****/blinky_custom_board/*****_build/_sysbuild && /opt/nordic/ncs/toolchains/b8efef2ad5/Cellar/cmake/3.21.0/bin/cmake -E true
-- west flash: using runner nrfjprog
-- runners.nrfjprog: reset after flashing requested
-- runners.nrfjprog: Flashing file: /Users/*****/Projects/GitHub/*****/blinky_custom_board/*****_build/merged.hex
[ #################### ]   1.651s | Erase file - Done erasing                                                          
[ #################### ]   0.361s | Program file - Done programming                                                    
[ #################### ]   0.283s | Verify file - Done verifying                                                       
Applying pin reset.
-- runners.nrfjprog: Board with serial number ********* flashed successfully.

I'm connecting with SWD selected on the RTT connection screen:

LOG: J-Link RTT Viewer V8.12a: Logging started.
LOG: Terminal 0 added.
LOG: Connecting to J-Link via USB...
LOG: Device "NRF5340_XXAA_APP" selected.
LOG: ConfigTargetSettings() start
LOG: ConfigTargetSettings() end - Took 2us
LOG: InitTarget() start
LOG: InitTarget() end - Took 1.51ms
LOG: Found SW-DP with ID 0x********
LOG: DPIDR: 0x********
LOG: CoreSight SoC-400 or earlier
LOG: AP map detection skipped. Manually configured AP map found.
LOG: AP[0]: AHB-AP (IDR: Not set, ADDR: 0x00000000)
LOG: AP[1]: AHB-AP (IDR: Not set, ADDR: 0x00000000)
LOG: AP[2]: MEM-AP (IDR: Not set, ADDR: 0x00000000)
LOG: AP[3]: MEM-AP (IDR: Not set, ADDR: 0x00000000)
LOG: AP[0]: Core found
LOG: AP[0]: AHB-AP ROM base: 0xE00FE000
LOG: CPUID register: 0x410FD214. Implementer code: 0x41 (ARM)
LOG: Feature set: Mainline
LOG: Cache: No cache
LOG: Found Cortex-M33 r0p4, Little endian.
LOG: FPUnit: 8 code (BP) slots and 0 literal slots
LOG: Security extension: implemented
LOG: Secure debug: enabled
LOG: CoreSight components:
LOG: ROMTbl[0] @ E00FE000
LOG: [0][0]: E00FF000 CID B105100D PID 000BB4C9 ROM Table
LOG: ROMTbl[1] @ E00FF000
LOG: [1][0]: E000E000 CID B105900D PID 000BBD21 DEVARCH 47702A04 DEVTYPE 00 Cortex-M33
LOG: [1][1]: E0001000 CID B105900D PID 000BBD21 DEVARCH 47701A02 DEVTYPE 00 DWT
LOG: [1][2]: E0002000 CID B105900D PID 000BBD21 DEVARCH 47701A03 DEVTYPE 00 FPB
LOG: [1][3]: E0000000 CID B105900D PID 000BBD21 DEVARCH 47701A01 DEVTYPE 43 ITM
LOG: [1][5]: E0041000 CID B105900D PID 002BBD21 DEVARCH 47724A13 DEVTYPE 13 ETM
LOG: [1][6]: E0042000 CID B105900D PID 000BBD21 DEVARCH 47701A14 DEVTYPE 14 CSS600-CTI
LOG: [0][1]: E0040000 CID B105900D PID 000BBD21 DEVARCH 00000000 DEVTYPE 11 TPIU
LOG: RTT Viewer connected.

I run in debug mode and get this:

After I press play nothing seems to happen. The place it stops shows this in the debugger:

=thread-group-added,id="i1"
=cmd-param-changed,param="pagination",value="off"
z_arm_reset () at /opt/nordic/ncs/v2.9.1/zephyr/arch/arm/core/cortex_m/reset.S:80
80	    movs.n r0, #0