Clarification on internal vs external crystal load capacitor configuration (nRF54L, NCS 2.9.0)

[Doris.chen]

Hello Nordic Team,

I previously asked about how to configure the internal load capacitance for the 32 MHz crystal on nRF54L, and I’ve successfully applied the solution provided — thank you!

However, since the internal load capacitor can only support up to 17 pF, we still need to add external capacitors to achieve the target load.

I’d like to clarify a few things regarding the hfxo configuration in the device tree:

This is what I currently see in my .dts file:

hfxo: hfxo {
	compatible = "nordic,nrf-hfxo";
	#clock-cells = <0>;
	clock-frequency = <0x1e84800>; // 32 MHz
	load-capacitors = "internal";
	load-capacitance-femtofarad = <0x4268>; // 17000 fF = 17 pF
};

My questions:

1. Does this mean the internal load capacitance is currently set to 17 pF?

2. If I add external capacitors (e.g., 5 pF) on the crystal lines, does that mean the total load seen by the crystal is 17 pF (internal) in parallel with 5 pF (external)?

3. If I switch the device tree setting to:

   hfxo: hfxo {
   	compatible = "nordic,nrf-hfxo";
   	#clock-cells = <0>;
   	clock-frequency = <0x1e84800>;
   	load-capacitors = "external";
   };
   

 

        Does that mean the SoC disables the internal capacitors, and only the external capacitors are used?

4. Is there anything else that I need to configure in software (e.g., in Kconfig or at runtime) to ensure the internal capacitors are fully disabled when using "external"?

Our goal is to ensure the correct load capacitance is applied to the crystal to achieve optimal frequency accuracy.

Thank you in advance for your clarification and support!

Best regards,
Doris

[AHaug]

Hi Doris,

Just fyi, have you seen chapter 11.9 w.r.t the Oscillators electrical specification in the nRF54L15 datasheet? https://docs-be.nordicsemi.com/bundle/ps_nrf54L15/page/pdf/nRF54L15_nRF54L10_nRF54L05_Datasheet_v0.8.pdf 

Here it's mentioned that the HFXO crystal should have a load capacitance of minimum 6 pF to maximum 9pF. CI=9F requires load capacitors of around 15pF, which is within the boundary of what the internal load capacitors can be configured to. You can see chapter 5.5.1 for computation of this.

If you assume that both load capacitors are identical and that there are no capacitance in the PCB lines you can simplify the equation to something like:

C_int = 2*CI - C_pin, where C_pin = 3pF

I suspect that this evaluation may have been skipped somewhat, since you've chosen 17pF? Please enlighten me in case I've misunderstood why you've chosen a crystal that has CI outside of the specification for the nRF54L15

Happy to help,
Andreas

[Doris.chen]

Hi Andreas,

Thanks a lot for the clarification — yes, I now realize that the 17 pF internal capacitance setting may be outside the recommended Cl range for the nRF54L15. The reason we used this crystal is because we have legacy modules based on earlier Nordic series, and we reused the same BOM in this prototype for evaluation.

I’ll double-check the Cl spec of our crystal and evaluate whether we should switch to a better-matched one in the next spin.

That said, for this design we’re now planning to add external capacitors to tune the load capacitance more accurately.

To support this, I’d like to confirm the software setting needed to fully disable the internal load capacitors, so that only the external capacitors take effect.

From the DTS, I see that I can set:

load-capacitors = "external";

Can you confirm that this setting completely disables the internal capacitors?

Is there any additional configuration needed in software (Zephyr or NCS), or is the DTS setting sufficient?

Thanks again for your helpful explanation!

Best regards,
Doris