nRF5340 with RV3028C7 external clock EVENTS_LFCLKSTARTED not triggering

[denis]

Our design has an nRF5340 with RV3028C7 to provide the 32 kHz clock via P0.00.

If I configure P0.00 as a digital input, I can see the pin toggling.

However, if I use the code below to try and switch from to the external clock, the EVENTS_LFCLKSTARTED doesn't happen.  Any idea why this would be?

NRF_CLOCK->LFCLKSRC = CLOCK_LFCLKSRC_SRC_LFXO << CLOCK_LFCLKSRC_SRC_Pos;

NRF_OSCILLATORS->XOSC32KI.INTCAP = OSCILLATORS_XOSC32KI_INTCAP_INTCAP_External << OSCILLATORS_XOSC32KI_INTCAP_INTCAP_Pos;

NRF_OSCILLATORS->XOSC32KI.BYPASS = OSCILLATORS_XOSC32KI_BYPASS_BYPASS_Enabled << OSCILLATORS_XOSC32KI_BYPASS_BYPASS_Pos;

NRF_P0->PIN_CNF[0] = GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos |

GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos |

GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos |

GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos;

NRF_P0->PIN_CNF[1] = GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos |

GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos |

GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos |

GPIO_PIN_CNF_INPUT_Disconnect<< GPIO_PIN_CNF_INPUT_Pos;

NRF_CLOCK->LFCLKALWAYSRUN = CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_AlwaysRun << CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Pos;

NRF_CLOCK->EVENTS_LFCLKSTARTED = 0;

NRF_CLOCK->TASKS_LFCLKSTART = 1;

uint32_t count = 0;

while (NRF_CLOCK->EVENTS_LFCLKSTARTED == 0) {

// wait for LFCLK to start

++count;

}

[runsiv]

Hi

I think you in order to use an external source, configure LFCLKSRC.SRC=LFXO as mention here. I'm not sure how Zephyr will handle changing clock source after init. So it might be an idea to configure zephyr to use the LFXO and create a function that sets your register in the init. 

Due to easter vacation here in Norway we will not be able to get back to you until next week. Thank you for your understanding

Regards

Runar

[denis]

The first line in the code above is setting  LFCLKSRC.SRC=LFXO.

I've tried using config properties to enable the LFXO also, but it hangs:

CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=y

CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=n

CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC_CALIBRATION=n

CONFIG_CLOCK_CONTROL_NRF_K32SRC_20PPM=y

 

arch_cpu_atomic_idle(unsigned int key) (/Users/denis/sandbox/pison/workspace/zephyr/arch/arm/core/cortex_m/cpu_idle.c:134)
k_cpu_atomic_idle(unsigned int key) (/Users/denis/sandbox/pison/workspace/zephyr/include/zephyr/kernel.h:6017)
lfclk_spinwait(enum nrf_lfclk_start_mode mode) (/Users/denis/sandbox/pison/workspace/zephyr/drivers/clock_control/clock_control_nrf.c:515)
z_nrf_clock_control_lf_on(enum nrf_lfclk_start_mode start_mode) (/Users/denis/sandbox/pison/workspace/zephyr/drivers/clock_control/clock_control_nrf.c:571)
sys_clock_driver_init() (/Users/denis/sandbox/pison/workspace/zephyr/drivers/timer/nrf_rtc_timer.c:766)
z_sys_init_run_level(enum init_level level) (/Users/denis/sandbox/pison/workspace/zephyr/kernel/init.c:374)
z_cstart() (/Users/denis/sandbox/pison/workspace/zephyr/kernel/init.c:782)
z_prep_c() (/Users/denis/sandbox/pison/workspace/zephyr/arch/arm/core/cortex_m/prep_c.c:209)
z_arm_reset() (/Users/denis/sandbox/pison/workspace/zephyr/arch/arm/core/cortex_m/reset.S:169)

So it seems that the LFXO isn't able to start for some reason.

If I setup P0.00 has a digital input and use DPPI to count a TIMER, then I do see a 32 kHz counting rate on that timer.  So the digital 32 kHz signal is present at P0.00.

[Vidar Berg]

Hello,

denis said:

I've tried using config properties to enable the LFXO also, but it hangs:

CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=y

This should work, but you will need to enable the bypass register before sys_clock_driver_init() is called on startup. You can achieve this by creating a custom "SYS_INIT" function in your application or in your board files similar to nordicsemi_nrf53_init(). The system clock should then be running off the external clock before the program reaches main().

NRF_P0->PIN_CNF[0] = GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos |

GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos |

GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos |

GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos;

NRF_P0->PIN_CNF[1] = GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos |

GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos |

GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos |

GPIO_PIN_CNF_INPUT_Disconnect<< GPIO_PIN_CNF_INPUT_Pos;

This will overwrite the existing configuration set here: https://github.com/zephyrproject-rtos/zephyr/blob/0b2d45595ea5ff39ec8df0c9ab43b2168beb4003/soc/nordic/nrf53/soc.c#L505 . When using the LFXO, the MCUSEL field shall be set to 'Peripheral':

Ref.  https://docs.nordicsemi.com/bundle/ps_nrf5340/page/chapters/oscillators/doc/oscillators.html#ariaid-title4