I am using XiP with partial code running from MX25. I am facing issue where I am getting hard faults when Erase is happening and at the same time the ISR from XiP region is triggered.
But in scenarios where Erase is happening and code executing from XIP is called then there is no hard fault, why?
This is my understanding until now:
ISRs are triggered asynchronously and immediately, regardless of flash state - whereas context switches happen under controlled condition, usually after the flash operation completes or from RAM/internal flash.
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ISRs are truly asynchronous and can interrupt a flash operation
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if an interrupt fires during a flash erase/write and the ISR is in external flash then:
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CPU tries to fetch instruction from external flash while it’s busy.
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Result: instruction fetch fails → Hard fault/ Bus fault
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Context switches are usually software driven
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Zephyr usually triggers a context switch:
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Inside the kernel thread loop
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After a system call (k_sleep(), k_yield() etc.)
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From a schedular decision after an interrupt returns.
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These typically happen after an ongoing flash operation finishes or from running internal flash or RAM.
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So when the schedular does k_context_swithc(), the instruction fetches for the context switch logic, and even the thread code, may not collide with a write/erase in progress.
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ISRs happen at any time
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if a flash write takes 40ms and a HW interrupt fires at 10ms:
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ISR jumps immediately to external flash
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Context switches don’t happen “at any time” - they occur between tasks, and Zephyr ensures (unless interrupted) that the system is in a consistent state.
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Stack and code location differences
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ISRs are more likely to run from external flash directly if not relocated
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Context switch mechanism/kernel code resides in internal flash.
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please let me know if there is gap in my understanding and also give the exact answer.
I am using Nordic 2.7.0 SDK
