Issue of Nordic AT45 DataFlash driver demo on (nrf9160dk/nrf9160) board.

[mark_82]

Hello,

I am trying to play the AT45 DataFlash driver by directly copying the sample code from nRF connect SDK v2.9.1 (C:\ncs\v2.9.1\zephyr\samples\drivers\spi_flash_at45).

Board target: nrf9160dk/nrf9160.

I did not modify anything in the sample code.

I used the nrf9160dk_nrf9160.overlay as default:

&pinctrl {
    spi3_default_alt: spi3_default_alt {
        group1 {
            psels = <NRF_PSEL(SPIM_SCK, 0, 11)>,
                <NRF_PSEL(SPIM_MOSI, 0, 12)>,
                <NRF_PSEL(SPIM_MISO, 0, 13)>;
        };
    };

    spi3_sleep_alt: spi3_sleep_alt {
        group1 {
            psels = <NRF_PSEL(SPIM_SCK, 0, 11)>,
                <NRF_PSEL(SPIM_MOSI, 0, 12)>,
                <NRF_PSEL(SPIM_MISO, 0, 13)>;
            low-power-enable;
        };
    };
};

&spi3 {
    pinctrl-0 = <&spi3_default_alt>;
    pinctrl-1 = <&spi3_sleep_alt>;
    pinctrl-names = "default", "sleep";
    cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>,
           <&gpio0 10 GPIO_ACTIVE_LOW>;

    at45db0: at45db041e@0 {
        compatible = "atmel,at45";
        reg = <0>;
        spi-max-frequency = <15000000>;
        jedec-id = [1f 24 00];
        size = <4194304>;
        sector-size = <65536>;
        block-size = <2048>;
        page-size = <256>;
        enter-dpd-delay = <2000>;
        exit-dpd-delay = <35000>;
        status = "disabled";
    };

    at45db1: at45db321e@1 {
        compatible = "atmel,at45";
        reg = <1>;
        spi-max-frequency = <15000000>;
        jedec-id = [1f 27 01];
        size = <33554432>;
        sector-size = <65536>;
        block-size = <4096>;
        page-size = <512>;
        use-udpd;
        enter-dpd-delay = <1000>;
        exit-dpd-delay = <180000>;
        status = "okay";
    };
};

&uart0 {
    /*
     * Only TX is used in this sample, so disable RX to prevent UART
     * receiver from being enabled and consuming power.
     */
    disable-rx;
};

For the hardware, I used AT45DB321E-MHF-T chip and wired it to my nRF9160 DK followed by above pin layout.

However, the diver is not working and cannot retrieve the correct data as expected:

[00:00:00.301,055] <err> spi_flash_at45: Wrong JEDEC ID: 00 00 00, expected: 1F 27 01
*** Booting nRF Connect SDK v2.9.1-60d0d6c8d42d ***
*** Using Zephyr OS v3.7.99-ca954a6216c9 ***
DataFlash sample on nrf9160dk
at45db321e@1: device not ready.

I used the oscilloscope to probe the CS pin. The signal was staying HIGH when the board power on but never go LOW when the board flashed.

Has anyone ever made this demo working?

[Vidar Berg]

Hello,

I don't have this device to test with, but I was able to get the CS to toggle by running the original sample project on my nRF9160 DK:

Did you probe p0.10? P0.20 is the CS assigned to the disabled at45db0 node.

Best regards,

Vidar

[mark_82]

Hello,

Now, I enable at45db0 node to status = "okay"; and disable at45db0 node to status = "disabled". The prob result are both of P0.10 and P0.20 are always staying HIGH and P0.11 (SCK) NO constant clocking output! It is the same result as I swap the node. Which pin did you probe on your waveform? P0.15 -> CS and P0.13 -> MOSI? Did you assign it to different pins when you running the original sample?

[mark_82]

Why does it matter? My CS P0.10 signal is always staying HIGH when I flash your hex. How can I check and change this pin configuration register to set as an output? 

[Vidar Berg]

I'm just trying to understand what I'm missing, as it doesn't make any sense that CS on P0.10 isn't being toggled when we're testing with the exact same firmware. 

mark_82 said:

How can I check and change this pin configuration register to set as an output? 

Start a debug session using our VS code extension and use the Peripherals View to view the GPIO configuration.

[mark_82]

Hi,

I found that my CS P0.10 -> PIN_CNF[10] is set as an INPUT. How can I set it as OUTPUT without changing the original code? Why is your default setting as OUTPUT? Any other pins I need to set to OUTPUT bare in mind?

[Vidar Berg]

The log output shows that the driver is now able to read the JEDEC ID from the chip. It also indicates that you have disabled the AT45DB1 node and instead enabled AT45DB0, which uses P0.20 for CS.

[mark_82]

Yes. The above output is when I swap two nodes. However, the original code I run was: 

 

and it was the same result as run your 1212.hex on my board. Do you mean I have to insure CS P0.10 is configured as an OUTPUT if I enabled AT45DB1 node (original code no changed)? Why my JEDEC ID read out is 00 00 00? What is your terminal result when you generating 1212.hex? 

[Vidar Berg]

When the JEDEC ID is read as 0, it means the chip did not respond (MISO kept low during the transfer). However, it’s interesting that you were able to communicate with the chip after swapping to the wrong node. Please ensure that the correct CS pin is connected.