In my application we have an nRF514L configured as an SPI target. Page 830 of the nRF54L datasheet (version 0.8, dated December 2024) documents that the SPIS peripheral requires a minimum of 1000 ns for the `CSN` to `SCK` setup time (t_SPIS,SUCSN). This is the minimum time from the falling edge of the chip select (`CSN`) input to the first rising edge of the clock (`SCK`) input. The footnote reads (in references to t_SPIS,SUCSN):
Excluding any start-up delay for the high frequency clock in low power mode
This is all well and fine, except that I cannot find in the datashet any specification (min/max/nominal) for the start-up delay of the high-frequency clock. Meaning it is not possible to determine what value of t_SPIS,SUCSN will ensure that I do not encounter data loss in my application.
Where can I find specifications for the HF clock startup delay?
