NRF3540: Duty cycle accuracy

Question

Hello,

I am working on a project using zephyr as well as the nrf5340 MCU. For this test, I am on the nrf5340dk.

My application requires I drive a PWM at 125khz. In my device tree, I setup the PWM as follows:

 pwm0_default: pwm0_default {
 group1 {
 psels = <NRF_PSEL(PWM_OUT0, 1, 6)>;
 nordic,drive-mode = <NRF_DRIVE_S0H1>;
 };
 };

 pwm0_sleep: pwm0_sleep {
 group1 {
 psels = <NRF_PSEL(PWM_OUT0, 1, 6)>;
 };
 };

With:

&pwm0 {
 pinctrl-0 = <&pwm0_default>;
 pinctrl-1 = <&pwm0_sleep>;
 pinctrl-names = "default", "sleep";
};

And:

The device application that uses it:

 pwms = <&pwm0 0 PWM_USEC(8) PWM_POLARITY_NORMAL>;

Additionally, I have a 32MHz external crystal.

In this instance, I have an application that effectively just turns on this PWM and nothing else.

If I hook up a logic analyzer to the pin, and I analyze the PWM , there is a "very" slight oscillation in the duty cycle.

Effectively, I fall from 49.93% duty cycle to 50% duty cycle up to 51.07% duty cycle, and back down. It is not necessarily periodic.

I wouldn't expect the duty cycle to be 50% exactly at all times, but there is concern from our hardware team that this noise is causing problems down the line for our application.

I want to do my due diligence and ask, is there anything related to registers that I could be missing to make the duty cycle cleaner? Or, alternatively, if there is a drive-mode that could potentially make the signal cleaner? Not sure if there is much to do, here.

I can provide more information as needed.