nRF54L15: RRAMC - Error handling

[Radoslaw Koppel]

Hi,

I am developing a project where we wish to use part of the RRAMC memory for logging purpose. The documentation show that the data endurance of RRAMC in nRF54L15 chips is at the level of 1e4. That is surprisingly low giving that the ReRAM chips on the market gives us 5e5 up to 1e6 erase - write cycles. Is it tested value or estimated by the technology. What to expect after exceeding this number of writes. I get it that Nordic chooses the solutions that focuses on low power more than endurance. Just wont to know what I can expect. Would I get any error notification or memory can just fail silently and the value that I read back would not match the value written?

It makes us little nervous about properly implementing file system with wear leveling and marking bad blocks.

I am reading through the documentation: docs.nordicsemi.com/.../rramc.html

Could you please elaborate more about EVENTS_ACCESSERROR event and ECC.ERRORADDR and ACCESSERRORADDR as the documentation I can find is quite limited in that topic and I also cannot find any usage of this registers in the samples. Especially ECC.ERRORADDR seems to be implemented only on HAL level, not used then in the drivers.

As I wish to detect memory failing as soon as possible there are my questions:

EVENTS_ACCESSERROR

When would be generated. May I expect it to be generated if the write fails? Or would it be generated only if the memory cannot be read? Would it be generated if the ECC fails to recover?

ACCESSERRIRADDR

Would it also cover ECC errors or ECC errors are present only in ECC.ERRORADDR.

ECC.ERRORADDR

Is is connected with EVENTS_ACCESSERROR? Documentation says that the event ECCERROR is generated. I cannot find ECCERROR event in the documentation.

[Radoslaw Koppel]

Additional question about Endurance.

In the documentation I can find:

nENDURANCE

Number of times a 128-bit word line can be written

10000

How should I read that?

Lets assume I am using unbuffered mode: What if I write 8 bits? Would it "use" my programming cycles only for this 8 bits or would it use from the whole 128 bit line? What if I write 8 bits 16 times to continuous addresses in the same line? Would I wear the whole line once of would I wear whole line 16 times?

[Einar Thorsrud]

Hi,

I need to check internally on most of this as it is not publically documented, and will get back to you. Regardign the additional question, all writes to the 128 bit word line counts, even if you do not flip the same bit more than once.

[Emil Lenngren]

I had a similar question here:  How to use RRAM ECC.ERRORADDR? 

Never got an answer...

[Einar Thorsrud]

I am sorry for the lack of response in the other thread. We are checking on this now, and I will update this thread, but it may take some days.

[Radoslaw Koppel]

 Emil Lenngren Yes - thank you for pointing this out. I had saw it while searching for my questions, but I believe that this is only the part of my question.

 Einar ThorsrudI wish to stress it out - there is something missing or bug in the documentation. I know that you are really busy right now - but it is hard to be accepted for such a question like the one from Emil to wait for 3 month to be responded. One of the reason of choosing the Nordic Chips is famous and extraordinary tech support. We are not asking to add some support nor to provide some new code. We are asking how your chips is working and where is the event described in the documentation.

Come on Nordic - we are working to bring the nRF54L to real life application and we would be more than happy to order rolls of chips when it is ready. But we also have to catch the market!