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  • Case ID: 345029
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nRF5340 ADC resolution vs conversion time

Wolfgang R

Hi all,

do different settings of SAADC RESOLUTION register affect Conversion Time tCONV?
I cannot find any dependency - the only value given for tCONV is 2 µs typ (7.29.12.1 SAADC Electrical Specification in PS v1.6).

If tCONV is independent of RESOLUTION: what would be the benefit of using less then max RESOLUTION?

Regards,
Wolfgang

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  • 0

    Hi,

    No, for the 52/53 series, the settings of SAADC RESOLUTION register does not have much affect on the conversion time tCONV ( typically it's around 2us). So your benefit would be the reduced data size and processing requirements, not increased sampling rate or lower latency.

    Though for the 54 series, this is different and the tCONV is lesser.

    Priyanka

  • 0 in reply to Priyanka

    Ok, sounds like we could get 200kHz even at 14 bit.

    However, we're still a bit concerned about terms like "not much effect" or "typically around 2 µs". This sounds a little vague.
    Is there any documentation about EXECT ADC timing?
    Q1: What clock source does the ADC run on? It seems to be a 16 MHz clock (assumption based on SAADC.SAMPLERATE.CC) - is it PCLK16M?

    Out plan is to let the ADC run in continuous mode triggered by internal timer with SAMPLERATE.CC=80 (5 µs), CH[n].CONFIG.TACQ=0 (3µs) plus 2µs tCONV resulting in 200 kHz sample rate, then Oversample 8x to get averaged results at 25 kHz rate. Not using Scan Mode.

    The actual rate need not be 25 kHz, but it must be stable (for signal processing).
    Q2: Is the ADC clock stable relative to PCLK16M, or does it vary, e.g. over temperature?

    Product spec S v1.6 says in 7.29.13 Performance factors: 
    "... startup times of regulators and references will contribute to variability."
    There doesn't seem to be any option the enable ADC hardware other than START, so it seems the ADC manages startup and shutdown of regulators and references automatically.
    Q3: Under which conditions do regulators and references start or shut down and restart so that their startup times come to effect?
    Q4: How long are these times?

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  • 0 in reply to Priyanka

    Ok, sounds like we could get 200kHz even at 14 bit.

    However, we're still a bit concerned about terms like "not much effect" or "typically around 2 µs". This sounds a little vague.
    Is there any documentation about EXECT ADC timing?
    Q1: What clock source does the ADC run on? It seems to be a 16 MHz clock (assumption based on SAADC.SAMPLERATE.CC) - is it PCLK16M?

    Out plan is to let the ADC run in continuous mode triggered by internal timer with SAMPLERATE.CC=80 (5 µs), CH[n].CONFIG.TACQ=0 (3µs) plus 2µs tCONV resulting in 200 kHz sample rate, then Oversample 8x to get averaged results at 25 kHz rate. Not using Scan Mode.

    The actual rate need not be 25 kHz, but it must be stable (for signal processing).
    Q2: Is the ADC clock stable relative to PCLK16M, or does it vary, e.g. over temperature?

    Product spec S v1.6 says in 7.29.13 Performance factors: 
    "... startup times of regulators and references will contribute to variability."
    There doesn't seem to be any option the enable ADC hardware other than START, so it seems the ADC manages startup and shutdown of regulators and references automatically.
    Q3: Under which conditions do regulators and references start or shut down and restart so that their startup times come to effect?
    Q4: How long are these times?

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