Cmake Errors while building code in nrf5340dk

when I try to build a code for integrating sensor in nRF 5340 dk, this error comes, I tried even after installing cmake manually from the cmake website https://cmake.org/, but unable to solve these errors , kindly help with a suitable solution.

SDK version 3.0.2

Parents
  • Hi,

    Check the "terminal" tab. In there you should find a more complete log. 
    Are you able to see from that log what is wrong?

    If not, can you copy it into Insert->Code here?

    Regards,
    Sigurd Hellesvik

  • Loading Zephyr default modules (Zephyr base (cached)).
    -- Application: C:/ncs/v3.0.2/nordictutorials/sensor
    -- CMake version: 3.21.0
    -- Cache files will be written to: C:/ncs/v3.0.2/zephyr/.cache
    -- Zephyr version: 4.0.99 (C:/ncs/v3.0.2/zephyr)
    -- Found west (found suitable version "1.2.0", minimum required is "0.14.0")
    -- Board: nrf5340dk, qualifiers: nrf5340/cpuapp
    -- Found host-tools: zephyr 0.17.0 (C:/ncs/toolchains/0b393f9e1b/opt/zephyr-sdk)
    -- Found toolchain: zephyr 0.17.0 (C:/ncs/toolchains/0b393f9e1b/opt/zephyr-sdk)
    -- Found BOARD.dts: C:/ncs/v3.0.2/zephyr/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp.dts
    -- Generated zephyr.dts: C:/ncs/v3.0.2/nordictutorials/sensor/build/sensor/zephyr/zephyr.dts
    -- Generated pickled edt: C:/ncs/v3.0.2/nordictutorials/sensor/build/sensor/zephyr/edt.pickle
    -- Generated zephyr.dts: C:/ncs/v3.0.2/nordictutorials/sensor/build/sensor/zephyr/zephyr.dts
    -- Generated devicetree_generated.h: C:/ncs/v3.0.2/nordictutorials/sensor/build/sensor/zephyr/include/generated/zephyr/devicetree_generated.h
    -- Including generated dts.cmake file: C:/ncs/v3.0.2/nordictutorials/sensor/build/sensor/zephyr/dts.cmake
    Parsing C:/ncs/v3.0.2/zephyr/Kconfig
    Loaded configuration 'C:/ncs/v3.0.2/nordictutorials/sensor/build/sensor/zephyr/.config'
    Merged configuration 'C:/ncs/v3.0.2/nordictutorials/sensor/build/sensor/zephyr/.config.sysbuild'
    No change to configuration in 'C:/ncs/v3.0.2/nordictutorials/sensor/build/sensor/zephyr/.config'
    No change to Kconfig header in 'C:/ncs/v3.0.2/nordictutorials/sensor/build/sensor/zephyr/include/generated/zephyr/autoconf.h'
    -- Configuring done
    -- Generating done
    -- Build files have been written to: C:/ncs/v3.0.2/nordictutorials/sensor/build/sensor
    [2/25] Building C object zephyr/soc/soc/nrf5340/CMakeFiles/soc__nordic.dir/validate_enabled_instances.c.obj
    FAILED: zephyr/soc/soc/nrf5340/CMakeFiles/soc__nordic.dir/validate_enabled_instances.c.obj 
    C:\ncs\toolchains\0b393f9e1b\opt\zephyr-sdk\arm-zephyr-eabi\bin\arm-zephyr-eabi-gcc.exe -DKERNEL -DK_HEAP_MEM_POOL_SIZE=0 -DNRF5340_XXAA_APPLICATION -DNRF_SKIP_FICR_NS_COPY_TO_RAM -DPICOLIBC_DOUBLE_PRINTF_SCANF -DUSE_PARTITION_MANAGER=1 -D__LINUX_ERRNO_EXTENSIONS__ -D__PROGRAM_START -D__ZEPHYR__=1 -IC:/ncs/v3.0.2/nordictutorials/sensor/build/sensor/zephyr/include/generated/zephyr -IC:/ncs/v3.0.2/zephyr/include -IC:/ncs/v3.0.2/nordictutorials/sensor/build/sensor/zephyr/include/generated -IC:/ncs/v3.0.2/zephyr/soc/nordic -IC:/ncs/v3.0.2/zephyr/soc/nordic/nrf53/. -IC:/ncs/v3.0.2/zephyr/soc/nordic/common/. -IC:/ncs/v3.0.2/nrf/include -IC:/ncs/v3.0.2/nrf/tests/include -IC:/ncs/v3.0.2/modules/hal/cmsis/CMSIS/Core/Include -IC:/ncs/v3.0.2/zephyr/modules/cmsis/. -IC:/ncs/v3.0.2/nrf/modules/hal_nordic/. -IC:/ncs/v3.0.2/modules/hal/nordic/nrfx -IC:/ncs/v3.0.2/modules/hal/nordic/nrfx/drivers/include -IC:/ncs/v3.0.2/modules/hal/nordic/nrfx/mdk -IC:/ncs/v3.0.2/zephyr/modules/hal_nordic/nrfx/. -isystem C:/ncs/v3.0.2/zephyr/lib/libc/common/include -isystem C:/ncs/v3.0.2/nrfxlib/crypto/nrf_cc312_platform/include -fno-strict-aliasing -Os -imacros C:/ncs/v3.0.2/nordictutorials/sensor/build/sensor/zephyr/include/generated/zephyr/autoconf.h -fno-common -g -gdwarf-4 -fdiagnostics-color=always -mcpu=cortex-m33 -mthumb -mabi=aapcs -mfp16-format=ieee -mtp=soft --sysroot=C:/ncs/toolchains/0b393f9e1b/opt/zephyr-sdk/arm-zephyr-eabi/arm-zephyr-eabi -imacros C:/ncs/v3.0.2/zephyr/include/zephyr/toolchain/zephyr_stdint.h -Wall -Wformat -Wformat-security -Wno-format-zero-length -Wdouble-promotion -Wno-pointer-sign -Wpointer-arith -Wexpansion-to-defined -Wno-unused-but-set-variable -Werror=implicit-int -fno-pic -fno-pie -fno-asynchronous-unwind-tables -ftls-model=local-exec -fno-reorder-functions --param=min-pagesize=0 -fno-defer-pop -fmacro-prefix-map=C:/ncs/v3.0.2/nordictutorials/sensor=CMAKE_SOURCE_DIR -fmacro-prefix-map=C:/ncs/v3.0.2/zephyr=ZEPHYR_BASE -fmacro-prefix-map=C:/ncs/v3.0.2=WEST_TOPDIR -ffunction-sections -fdata-sections -specs=picolibc.specs -std=c99 -MD -MT zephyr/soc/soc/nrf5340/CMakeFiles/soc__nordic.dir/validate_enabled_instances.c.obj -MF zephyr\soc\soc\nrf5340\CMakeFiles\soc__nordic.dir\validate_enabled_instances.c.obj.d -o zephyr/soc/soc/nrf5340/CMakeFiles/soc__nordic.dir/validate_enabled_instances.c.obj -c C:/ncs/v3.0.2/zephyr/soc/nordic/validate_enabled_instances.c
    In file included from C:/ncs/v3.0.2/zephyr/include/zephyr/toolchain.h:50,
                     from C:/ncs/v3.0.2/zephyr/include/zephyr/kernel_includes.h:23,
                     from C:/ncs/v3.0.2/zephyr/include/zephyr/kernel.h:17,
                     from C:/ncs/v3.0.2/zephyr/soc/nordic/validate_enabled_instances.c:7:
    C:/ncs/v3.0.2/zephyr/include/zephyr/toolchain/gcc.h:87:36: error: static assertion failed: "Only one of the following peripherals can be enabled: SPI0, SPIM0, SPIS0, TWI0, TWIM0, TWIS0, UARTE0. Check nodes with status \"okay\" in zephyr.dts."
       87 | #define BUILD_ASSERT(EXPR, MSG...) _Static_assert((EXPR), "" MSG)
          |                                    ^~~~~~~~~~~~~~
    C:/ncs/v3.0.2/zephyr/soc/nordic/validate_enabled_instances.c:50:1: note: in expansion of macro 'BUILD_ASSERT'
       50 | BUILD_ASSERT(CHECK(0), MSG(0));
          | ^~~~~~~~~~~~
    [15/25] Building C object zephyr/kernel/CMakeFiles/kernel.dir/sched.c.obj
    ninja: build stopped: subcommand failed.
    FATAL ERROR: command exited with status 1: 'C:\ncs\toolchains\0b393f9e1b\opt\bin\cmake.EXE' --build C:/ncs/v3.0.2/nordictutorials/sensor/build/sensor
    
     *  The terminal process terminated with exit code: 1. 
     *  Terminal will be reused by tasks, press any key to close i
    Thank you , now when I'm trying to interface sensor,First time it was built but displayed  sensor not detected,but from second time build error is happening, shall I share my .overlay and .dts files 

    Regards

    Gouri.K 

  • &spi4 {
        compatible = "nordic,nrf-spim";
    	status = "okay";
    	pinctrl-0 = <&spi4_default>;
    	pinctrl-1 = <&spi4_sleep>;
    	pinctrl-names = "default", "sleep";
    	cs-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH >;
    	 lsm6dsl:lsm6dsl@0 {
    		compatible = "st,lsm6dsl";
    		reg = <0>;
    		spi-max-frequency = <10000000>; 
    	};
    };
    &pinctrl {
    	spi4_default: spi4_default {
    		group1 {
    				psels = <NRF_PSEL(SPIM_SCK, 1, 15)>,
    						<NRF_PSEL(SPIM_MOSI, 1, 13)>,
    						<NRF_PSEL(SPIM_MISO, 1, 14)>;
    		};
    	};
    
    	spi4_sleep: spi4_sleep {
    		group1 {
    				psels = <NRF_PSEL(SPIM_SCK, 1,15)>,
                <NRF_PSEL(SPIM_MOSI, 1, 13)>,
                <NRF_PSEL(SPIM_MISO, 1, 14)>;
                low-power-enable;
    		};
    	};
    };
    
    

    This is the overlay file we had created (nrf5340dk_nrf5340_cpuapp.overlay).For me only .defconfig files are visible. And is it possible to edit .dts files, saw in one tutorial that we should not edit .dts device tree files
  • The delay in answering here is due to limited staff during this period. I will try to get back to you in two or three weeks. Sorry for the inconvenience. 

  • Hello Gouri,

    Sigurd will be away for some time, and I’ll be looking into this issue in the meantime.

    Could you please update me on the current status of the issue? The last update I can see here is from a few weeks ago. Are you still facing the CMake issue you previously reported, or is it something else I should look into?

    Gouri said:
    his is the overlay file we had created (nrf5340dk_nrf5340_cpuapp.overlay).For me only .defconfig files are visible. And is it possible to edit .dts files, saw in one tutorial that we should not edit .dts device tree files

    If you are asking about the base DTS files inside the SDK, yes, it’s not recommended to edit those directly. Instead, it's better to use overlay files in your application. This is mainly because if you modify SDK-provided .dts files for official boards, your changes will be lost during an SDK update.

    Kind Regards,

    Abhijith

  • Hello,Thankyou Abhijith, we were able to communicate to accelerometer and get data, the current issue is we are unable to communicate with flash through QSPI.
    We have developed a custom board featuring the BL5340 SoC, with the W25Q01JV external flash connected via QSPI.

    At present, we are encountering an issue where the flash does not respond to any of the standard opcodes such as JEDEC ID, Read, Erase, Write.

    For reference, we have attached the relevant code.

    During debugging with a DSO, we observed that only the Chip Select (CS) line goes low when communication is initiated. However, all other QSPI lines—including the clock—remain idle with no signal activity or transitions.

    We would greatly appreciate any guidance or suggestions you may have to help us resolve this issue.We are attaching our main.c and overlay file.

    / {
        chosen {
            zephyr,console = &uart0;
            zephyr,shell-uart = &uart0;
            zephyr,uart-mcumgr = &uart0;
        };
    
        aliases {
            i2c-mpu6050 = &i2c_mpu6050;
            i2c-ccs811 = &i2c_ccs811;
        };
    };
    
    &i2c1 {
        status = "okay";
        i2c_mpu6050: mpu6050@68 {
            status = "okay";
            compatible = "invensense,mpu6050";
            reg = <0x68>;
        };
        i2c_ccs811: ccs811@5b {
            status = "okay";
            compatible = "ams,ccs811";
            reg = <0x5b>;
        };
    };
    
    &spi2 {
        status = "disabled"; /* Avoid pin conflicts */
    };
    
    &spi3 {
        status = "disabled"; /* Avoid pin conflicts */
    };
    
    &spi4 {
        status = "disabled"; /* Avoid pin conflicts */
    };
    /delete-node/&{/soc/peripheral@50000000/i2c@9000/tca9538@70/};
    /delete-node/&{/buttons/};  
        /delete-node/&{/leds/};  
            /delete-node/&{/aliases/};
    // &qspi {
    //     status = "okay";
    //     pinctrl-0 = <&qspi_default>;
    //     pinctrl-1 = <&qspi_sleep>;
    //     pinctrl-names = "default", "sleep";
    //     w25q01jv: w25q01jv@0 {
    //         compatible = "nordic,qspi-nor";
    //         reg = <0>;
    //         writeoc = "pp4io"; /* 0x32 - Quad Page Program */
    //         readoc = "read4io"; /* 0xEB - Fast Read Quad I/O */
    //         sck-frequency = <8000000>;
    //         jedec-id = [ef 40 21];
    //         size = <0x8000000>; /* 128 MB */
    //         has-dpd;
    //         t-enter-dpd = <10000>;
    //         t-exit-dpd = <35000>;
    //         address-size-32;
    //     };
    // };
    
    // &flash0 {
    //     partitions {
    //         compatible = "fixed-partitions";
    //         #address-cells = <1>;
    //         #size-cells = <1>;
    
    //         /* Bootloader partition (64 KB) */
    //         boot_partition: partition@0 {
    //             label = "mcuboot";
    //             reg = <0x00000000 0x00010000>;
    //         };
    
    //         /* Primary image slot (640 KB) */
    //         slot0_partition: partition@10000 {
    //             label = "image-0";
    //             reg = <0x00010000 0x000a0000>;
    //         };
    
    //         /* Non-secure image slot (256 KB) */
    //         slot0_ns_partition: partition@b0000 {
    //             label = "image-0-nonsecure";
    //             reg = <0x000b0000 0x00040000>;
    //         };
    
    //         /* Storage partition (32 KB) */
    //         storage_partition: partition@f8000 {
    //             label = "storage";
    //             reg = <0x000f8000 0x00008000>;
    //         };
    //     };
    // };
    
    // &w25q01jv {
    //     partitions {
    //         compatible = "fixed-partitions";
    //         #address-cells = <1>;
    //         #size-cells = <1>;
    
    //         /* Secondary image slot (640 KB) */
    //         slot1_partition: partition@0 {
    //             label = "image-1";
    //             reg = <0x00000000 0x000a0000>;
    //         };
    
    //         /* Non-secure secondary image slot (256 KB) */
    //         slot1_ns_partition: partition@a0000 {
    //             label = "image-1-nonsecure";
    //             reg = <0x000a0000 0x00040000>;
    //         };
    
    //         /* Scratch partition (128 KB) */
    //         scratch_partition: partition@e0000 {
    //             label = "image-scratch";
    //             reg = <0x000e0000 0x00020000>;
    //         };
    
    //         /* LittleFS storage (7 MB) */
    //         lfs_partition: partition@100000 {
    //             label = "lfs_storage";
    //             reg = <0x00100000 0x00700000>;
    //         };
    //     };
    // };

    Kind regards

    Gouri.k

    #include <zephyr/kernel.h>
    #include <zephyr/logging/log.h>
    #include <nrfx_qspi.h>
    #include <hal/nrf_qspi.h>
    #include <string.h>
    #include <nrfx_qspi.h>
    
    
    LOG_MODULE_REGISTER(qspi_flash_demo, LOG_LEVEL_DBG);
    
    // Test address in lfs_partition (7 MB, safe for testing)
    #define TEST_ADDR  0x00100000
    #define SECTOR_SIZE 4096
    
    static const nrfx_qspi_config_t qspi_config = {
        .xip_offset = 0,
        .pins = {
            .sck_pin = 17, // P0.17
            .csn_pin = 18, // P0.18
            .io0_pin = 13, // P0.13
            .io1_pin = 14, // P0.14
            .io2_pin = 15, // P0.15
            .io3_pin = 16, // P0.16
        },
        .prot_if = {
            .readoc   = NRF_QSPI_READOC_READ4IO, // 0xEB - Fast Read Quad I/O
            .writeoc  = NRF_QSPI_WRITEOC_PP4IO,  // 0x32 - Quad Page Program
            .addrmode = NRF_QSPI_ADDRMODE_24BIT,
            .dpmconfig = false,
        },
        .phy_if = {
            .sck_delay = 1,
            .dpmen     = false,
        },
        .irq_priority = 7, // Lowest priority for nRF5340
    };
    
    static void qspi_flash_read_jedec_id(void)
    {
        uint8_t jedec_id[3];
        nrf_qspi_cinstr_conf_t cfg = {
            .opcode = 0x9F, // JEDEC ID command
            .length = NRF_QSPI_CINSTR_LEN_4B,
            .io2_level = true,
            .io3_level = true,
            .wipwait = true,
            .wren = false,
        };
        nrfx_err_t err = nrfx_qspi_cinstr_xfer(&cfg, NULL, jedec_id);
        if (err == NRFX_SUCCESS) {
            LOG_INF("JEDEC ID: %02x %02x %02x", jedec_id[0], jedec_id[1], jedec_id[2]);
        } else {
            LOG_ERR("Failed to read JEDEC ID: 0x%x", err);
        }
    }
    
    // Manual reset sequence for W25Q01JV
    static int send_qspi_reset_cmds(void)
    {
        nrfx_err_t ret;
    
        nrfx_qspi_cinstr_conf_t cinstr_cfg = {
            .opcode    = 0x66,  // Enable Reset
            .length    = NRFX_QSPI_CINSTR_LEN_1B,
            .io2_level = true,
            .io3_level = true,
            .wipwait   = true,
            .wren      = false
        };
    
        ret = nrfx_qspi_cinstr_xfer(&cinstr_cfg, NULL, NULL);
        if (ret != NRFX_SUCCESS) {
            LOG_ERR("QSPI reset enable (0x66) failed: 0x%x", ret);
            return -EIO;
        }
    
        // Wait 100us (per datasheet)
        k_busy_wait(100);
    
        cinstr_cfg.opcode = 0x99;  // Reset Device
        ret = nrfx_qspi_cinstr_xfer(&cinstr_cfg, NULL, NULL);
        if (ret != NRFX_SUCCESS) {
            LOG_ERR("QSPI reset (0x99) failed: 0x%x", ret);
            return -EIO;
        }
    
        // Wait 30ms after reset (per datasheet)
        k_msleep(30);
        return 0;
    }
    
    static void qspi_flash_read_status_reg(void)
    {
        uint8_t status_reg;
        nrf_qspi_cinstr_conf_t cfg = {
            .opcode = 0x05, // Read Status Register-1
            .length = NRF_QSPI_CINSTR_LEN_2B,
            .io2_level = true,
            .io3_level = true,
            .wipwait = true,
            .wren = false,
        };
        nrfx_err_t err = nrfx_qspi_cinstr_xfer(&cfg, NULL, &status_reg);
        if (err == NRFX_SUCCESS) {
            LOG_INF("Status Register-1: 0x%02x", status_reg);
        } else {
            LOG_ERR("Failed to read Status Register-1: 0x%x", err);
        }
    }
    
    int main(void)
    {
        while(1){
        LOG_INF("Starting firmware...");
        LOG_INF("QSPI Flash Test Start");
    
        // Log stack usage
        extern uint32_t __stack_chk_guard;
        uint32_t stack_remaining = (uint32_t)&__stack_chk_guard - (uint32_t)__get_PSP();
        LOG_INF("Stack remaining: %u bytes", stack_remaining);
    
        // Log QSPI peripheral status before initialization
        LOG_INF("QSPI STATUS: 0x%08x", NRF_QSPI->STATUS);
        LOG_INF("QSPI ENABLE: 0x%08x", NRF_QSPI->ENABLE);
    
        // Delay to allow system stabilization
        k_msleep(100);
    
         nrfx_err_t ret = nrfx_qspi_init(&qspi_config, NULL, NULL);
        if (ret != NRFX_SUCCESS) {
            LOG_ERR("QSPI init failed: 0x%x", ret);
            LOG_INF("QSPI STATUS after init: 0x%08x", NRF_QSPI->STATUS);
            return -1;
        }
    
        k_msleep(100); // Additional delay for flash chip stabilization
        LOG_INF("QSPI initialized");
    
        nrf_qspi_cinstr_conf_t wake_cmd = {
        .opcode = 0xAB,
        .length = NRF_QSPI_CINSTR_LEN_1B,
        .io2_level = true,
        .io3_level = true,
        .wipwait = true,
        .wren = false,
    };
    nrfx_qspi_cinstr_xfer(&wake_cmd, NULL, NULL);
    k_msleep(100); // give it time
    
    //manual Reset 
    qspi_flash_manual_reset();
    
       
    
        // Verify flash chip presence with JEDEC ID
        qspi_flash_read_jedec_id();
    
        // Check status register to ensure flash is ready
        qspi_flash_read_status_reg();
    
        // Enable write operations
        nrf_qspi_cinstr_conf_t wren_cfg = {
            .opcode = 0x06, // Write Enable
            .length = NRF_QSPI_CINSTR_LEN_1B,
            .io2_level = true,
            .io3_level = true,
            .wipwait = true,
            .wren = false,
        };
        ret = nrfx_qspi_cinstr_xfer(&wren_cfg, NULL, NULL);
        if (ret != NRFX_SUCCESS) {
            LOG_ERR("Write Enable failed: 0x%x", ret);
            return -1;
        }
    
        // Erase 4KB sector
        LOG_INF("Erasing 4KB sector at address 0x%08x...", TEST_ADDR);
        ret = nrfx_qspi_erase(NRF_QSPI_ERASE_LEN_4KB, TEST_ADDR);
        if (ret != NRFX_SUCCESS) {
            LOG_ERR("Erase failed: 0x%x", ret);
            return -1;
        }
    
        // Wait for erase completion
        ret = nrfx_qspi_mem_busy_check();
        if (ret != NRFX_SUCCESS) {
            LOG_ERR("Erase busy check failed: 0x%x", ret);
            return -1;
        }
        LOG_INF("Erase completed");
    
        // Read back 4KB to verify all bytes are 0xFF
        uint8_t read_buf[SECTOR_SIZE];
        memset(read_buf, 0, SECTOR_SIZE);
        ret = nrfx_qspi_read(read_buf, SECTOR_SIZE, TEST_ADDR);
        if (ret != NRFX_SUCCESS) {
            LOG_ERR("Read failed: 0x%x", ret);
            return -1;
        }
    
        // Verify all bytes are 0xFF
        bool erased = true;
        for (uint32_t i = 0; i < SECTOR_SIZE; i++) {
            if (read_buf[i] != 0xFF) {
                LOG_ERR("Erase verification failed at offset %d: read 0x%02x, expected 0xFF", i, read_buf[i]);
                erased = false;
                break;
            }
        }
    
        if (erased) {
            LOG_INF("Erase test PASSED: Sector at 0x%08x is all 0xFF", TEST_ADDR);
        } else {
            LOG_ERR("Erase test FAILED: Sector at 0x%08x not fully erased", TEST_ADDR);
        }
    }
        return 0;
    
    }

Reply
  • Hello,Thankyou Abhijith, we were able to communicate to accelerometer and get data, the current issue is we are unable to communicate with flash through QSPI.
    We have developed a custom board featuring the BL5340 SoC, with the W25Q01JV external flash connected via QSPI.

    At present, we are encountering an issue where the flash does not respond to any of the standard opcodes such as JEDEC ID, Read, Erase, Write.

    For reference, we have attached the relevant code.

    During debugging with a DSO, we observed that only the Chip Select (CS) line goes low when communication is initiated. However, all other QSPI lines—including the clock—remain idle with no signal activity or transitions.

    We would greatly appreciate any guidance or suggestions you may have to help us resolve this issue.We are attaching our main.c and overlay file.

    / {
        chosen {
            zephyr,console = &uart0;
            zephyr,shell-uart = &uart0;
            zephyr,uart-mcumgr = &uart0;
        };
    
        aliases {
            i2c-mpu6050 = &i2c_mpu6050;
            i2c-ccs811 = &i2c_ccs811;
        };
    };
    
    &i2c1 {
        status = "okay";
        i2c_mpu6050: mpu6050@68 {
            status = "okay";
            compatible = "invensense,mpu6050";
            reg = <0x68>;
        };
        i2c_ccs811: ccs811@5b {
            status = "okay";
            compatible = "ams,ccs811";
            reg = <0x5b>;
        };
    };
    
    &spi2 {
        status = "disabled"; /* Avoid pin conflicts */
    };
    
    &spi3 {
        status = "disabled"; /* Avoid pin conflicts */
    };
    
    &spi4 {
        status = "disabled"; /* Avoid pin conflicts */
    };
    /delete-node/&{/soc/peripheral@50000000/i2c@9000/tca9538@70/};
    /delete-node/&{/buttons/};  
        /delete-node/&{/leds/};  
            /delete-node/&{/aliases/};
    // &qspi {
    //     status = "okay";
    //     pinctrl-0 = <&qspi_default>;
    //     pinctrl-1 = <&qspi_sleep>;
    //     pinctrl-names = "default", "sleep";
    //     w25q01jv: w25q01jv@0 {
    //         compatible = "nordic,qspi-nor";
    //         reg = <0>;
    //         writeoc = "pp4io"; /* 0x32 - Quad Page Program */
    //         readoc = "read4io"; /* 0xEB - Fast Read Quad I/O */
    //         sck-frequency = <8000000>;
    //         jedec-id = [ef 40 21];
    //         size = <0x8000000>; /* 128 MB */
    //         has-dpd;
    //         t-enter-dpd = <10000>;
    //         t-exit-dpd = <35000>;
    //         address-size-32;
    //     };
    // };
    
    // &flash0 {
    //     partitions {
    //         compatible = "fixed-partitions";
    //         #address-cells = <1>;
    //         #size-cells = <1>;
    
    //         /* Bootloader partition (64 KB) */
    //         boot_partition: partition@0 {
    //             label = "mcuboot";
    //             reg = <0x00000000 0x00010000>;
    //         };
    
    //         /* Primary image slot (640 KB) */
    //         slot0_partition: partition@10000 {
    //             label = "image-0";
    //             reg = <0x00010000 0x000a0000>;
    //         };
    
    //         /* Non-secure image slot (256 KB) */
    //         slot0_ns_partition: partition@b0000 {
    //             label = "image-0-nonsecure";
    //             reg = <0x000b0000 0x00040000>;
    //         };
    
    //         /* Storage partition (32 KB) */
    //         storage_partition: partition@f8000 {
    //             label = "storage";
    //             reg = <0x000f8000 0x00008000>;
    //         };
    //     };
    // };
    
    // &w25q01jv {
    //     partitions {
    //         compatible = "fixed-partitions";
    //         #address-cells = <1>;
    //         #size-cells = <1>;
    
    //         /* Secondary image slot (640 KB) */
    //         slot1_partition: partition@0 {
    //             label = "image-1";
    //             reg = <0x00000000 0x000a0000>;
    //         };
    
    //         /* Non-secure secondary image slot (256 KB) */
    //         slot1_ns_partition: partition@a0000 {
    //             label = "image-1-nonsecure";
    //             reg = <0x000a0000 0x00040000>;
    //         };
    
    //         /* Scratch partition (128 KB) */
    //         scratch_partition: partition@e0000 {
    //             label = "image-scratch";
    //             reg = <0x000e0000 0x00020000>;
    //         };
    
    //         /* LittleFS storage (7 MB) */
    //         lfs_partition: partition@100000 {
    //             label = "lfs_storage";
    //             reg = <0x00100000 0x00700000>;
    //         };
    //     };
    // };

    Kind regards

    Gouri.k

    #include <zephyr/kernel.h>
    #include <zephyr/logging/log.h>
    #include <nrfx_qspi.h>
    #include <hal/nrf_qspi.h>
    #include <string.h>
    #include <nrfx_qspi.h>
    
    
    LOG_MODULE_REGISTER(qspi_flash_demo, LOG_LEVEL_DBG);
    
    // Test address in lfs_partition (7 MB, safe for testing)
    #define TEST_ADDR  0x00100000
    #define SECTOR_SIZE 4096
    
    static const nrfx_qspi_config_t qspi_config = {
        .xip_offset = 0,
        .pins = {
            .sck_pin = 17, // P0.17
            .csn_pin = 18, // P0.18
            .io0_pin = 13, // P0.13
            .io1_pin = 14, // P0.14
            .io2_pin = 15, // P0.15
            .io3_pin = 16, // P0.16
        },
        .prot_if = {
            .readoc   = NRF_QSPI_READOC_READ4IO, // 0xEB - Fast Read Quad I/O
            .writeoc  = NRF_QSPI_WRITEOC_PP4IO,  // 0x32 - Quad Page Program
            .addrmode = NRF_QSPI_ADDRMODE_24BIT,
            .dpmconfig = false,
        },
        .phy_if = {
            .sck_delay = 1,
            .dpmen     = false,
        },
        .irq_priority = 7, // Lowest priority for nRF5340
    };
    
    static void qspi_flash_read_jedec_id(void)
    {
        uint8_t jedec_id[3];
        nrf_qspi_cinstr_conf_t cfg = {
            .opcode = 0x9F, // JEDEC ID command
            .length = NRF_QSPI_CINSTR_LEN_4B,
            .io2_level = true,
            .io3_level = true,
            .wipwait = true,
            .wren = false,
        };
        nrfx_err_t err = nrfx_qspi_cinstr_xfer(&cfg, NULL, jedec_id);
        if (err == NRFX_SUCCESS) {
            LOG_INF("JEDEC ID: %02x %02x %02x", jedec_id[0], jedec_id[1], jedec_id[2]);
        } else {
            LOG_ERR("Failed to read JEDEC ID: 0x%x", err);
        }
    }
    
    // Manual reset sequence for W25Q01JV
    static int send_qspi_reset_cmds(void)
    {
        nrfx_err_t ret;
    
        nrfx_qspi_cinstr_conf_t cinstr_cfg = {
            .opcode    = 0x66,  // Enable Reset
            .length    = NRFX_QSPI_CINSTR_LEN_1B,
            .io2_level = true,
            .io3_level = true,
            .wipwait   = true,
            .wren      = false
        };
    
        ret = nrfx_qspi_cinstr_xfer(&cinstr_cfg, NULL, NULL);
        if (ret != NRFX_SUCCESS) {
            LOG_ERR("QSPI reset enable (0x66) failed: 0x%x", ret);
            return -EIO;
        }
    
        // Wait 100us (per datasheet)
        k_busy_wait(100);
    
        cinstr_cfg.opcode = 0x99;  // Reset Device
        ret = nrfx_qspi_cinstr_xfer(&cinstr_cfg, NULL, NULL);
        if (ret != NRFX_SUCCESS) {
            LOG_ERR("QSPI reset (0x99) failed: 0x%x", ret);
            return -EIO;
        }
    
        // Wait 30ms after reset (per datasheet)
        k_msleep(30);
        return 0;
    }
    
    static void qspi_flash_read_status_reg(void)
    {
        uint8_t status_reg;
        nrf_qspi_cinstr_conf_t cfg = {
            .opcode = 0x05, // Read Status Register-1
            .length = NRF_QSPI_CINSTR_LEN_2B,
            .io2_level = true,
            .io3_level = true,
            .wipwait = true,
            .wren = false,
        };
        nrfx_err_t err = nrfx_qspi_cinstr_xfer(&cfg, NULL, &status_reg);
        if (err == NRFX_SUCCESS) {
            LOG_INF("Status Register-1: 0x%02x", status_reg);
        } else {
            LOG_ERR("Failed to read Status Register-1: 0x%x", err);
        }
    }
    
    int main(void)
    {
        while(1){
        LOG_INF("Starting firmware...");
        LOG_INF("QSPI Flash Test Start");
    
        // Log stack usage
        extern uint32_t __stack_chk_guard;
        uint32_t stack_remaining = (uint32_t)&__stack_chk_guard - (uint32_t)__get_PSP();
        LOG_INF("Stack remaining: %u bytes", stack_remaining);
    
        // Log QSPI peripheral status before initialization
        LOG_INF("QSPI STATUS: 0x%08x", NRF_QSPI->STATUS);
        LOG_INF("QSPI ENABLE: 0x%08x", NRF_QSPI->ENABLE);
    
        // Delay to allow system stabilization
        k_msleep(100);
    
         nrfx_err_t ret = nrfx_qspi_init(&qspi_config, NULL, NULL);
        if (ret != NRFX_SUCCESS) {
            LOG_ERR("QSPI init failed: 0x%x", ret);
            LOG_INF("QSPI STATUS after init: 0x%08x", NRF_QSPI->STATUS);
            return -1;
        }
    
        k_msleep(100); // Additional delay for flash chip stabilization
        LOG_INF("QSPI initialized");
    
        nrf_qspi_cinstr_conf_t wake_cmd = {
        .opcode = 0xAB,
        .length = NRF_QSPI_CINSTR_LEN_1B,
        .io2_level = true,
        .io3_level = true,
        .wipwait = true,
        .wren = false,
    };
    nrfx_qspi_cinstr_xfer(&wake_cmd, NULL, NULL);
    k_msleep(100); // give it time
    
    //manual Reset 
    qspi_flash_manual_reset();
    
       
    
        // Verify flash chip presence with JEDEC ID
        qspi_flash_read_jedec_id();
    
        // Check status register to ensure flash is ready
        qspi_flash_read_status_reg();
    
        // Enable write operations
        nrf_qspi_cinstr_conf_t wren_cfg = {
            .opcode = 0x06, // Write Enable
            .length = NRF_QSPI_CINSTR_LEN_1B,
            .io2_level = true,
            .io3_level = true,
            .wipwait = true,
            .wren = false,
        };
        ret = nrfx_qspi_cinstr_xfer(&wren_cfg, NULL, NULL);
        if (ret != NRFX_SUCCESS) {
            LOG_ERR("Write Enable failed: 0x%x", ret);
            return -1;
        }
    
        // Erase 4KB sector
        LOG_INF("Erasing 4KB sector at address 0x%08x...", TEST_ADDR);
        ret = nrfx_qspi_erase(NRF_QSPI_ERASE_LEN_4KB, TEST_ADDR);
        if (ret != NRFX_SUCCESS) {
            LOG_ERR("Erase failed: 0x%x", ret);
            return -1;
        }
    
        // Wait for erase completion
        ret = nrfx_qspi_mem_busy_check();
        if (ret != NRFX_SUCCESS) {
            LOG_ERR("Erase busy check failed: 0x%x", ret);
            return -1;
        }
        LOG_INF("Erase completed");
    
        // Read back 4KB to verify all bytes are 0xFF
        uint8_t read_buf[SECTOR_SIZE];
        memset(read_buf, 0, SECTOR_SIZE);
        ret = nrfx_qspi_read(read_buf, SECTOR_SIZE, TEST_ADDR);
        if (ret != NRFX_SUCCESS) {
            LOG_ERR("Read failed: 0x%x", ret);
            return -1;
        }
    
        // Verify all bytes are 0xFF
        bool erased = true;
        for (uint32_t i = 0; i < SECTOR_SIZE; i++) {
            if (read_buf[i] != 0xFF) {
                LOG_ERR("Erase verification failed at offset %d: read 0x%02x, expected 0xFF", i, read_buf[i]);
                erased = false;
                break;
            }
        }
    
        if (erased) {
            LOG_INF("Erase test PASSED: Sector at 0x%08x is all 0xFF", TEST_ADDR);
        } else {
            LOG_ERR("Erase test FAILED: Sector at 0x%08x not fully erased", TEST_ADDR);
        }
    }
        return 0;
    
    }

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