nrf51422 decoupling capacitors

[tuv0k]

Hi,

I usually use electronics.stackexchange.com/.../15143 approach for decoupling capacitors and until now I had much better EMI performances.

I make sure that tracks between decoupling capacitors and MCU never run across main ground plane. GNDs are all connected together and tied with global ground plane in exactly one point.

However, nrf51422 Product specification v3.1. says:

Long power supply lines on the PCB should be avoided. All device grounds, VDD connections, and VDD bypass capacitors must be connected as close as possible to the IC. For a PCB with a topside RF ground plane, the VSS pins should be connected directly to the ground plane. For a PCB with a bottom ground plane, the best technique is to have via holes as close as possible to the VSS pads. A minimum of one via hole should be used for each VSS pin.

Would mine approach result in a problem with nrf51422?

[Fredrik Sundt Brynhildsvoll]

Hello,

the approach of connecting grounds together in a local plane and then connecting this again to the global plane in one point will generally generate less noise in the ground plane. But due to the long lines there will be an increase in the inductance between the chip vss pins and the ground plane. For a microcontroller without an radio this is usually not a problem and it is good practice. This is not the case for our chips.

The antenna use the ground plane as a reference and a relatively small inductance will at 2.4GHz function as an open circuit, meaning the antenna will have problems seeing the ground.

So there is a trade off between the noise in the ground plane and how good the RF performance of the design will be. If your system is not very sensitive to noise in the ground (because you have sensitive analog devices connected) I would recommend to use the guidelines in the product specification.

We have also written a tutorial which describe general PCB guidelines for the nrf51 chip. You can pick up a lot of tips on how a circuit should be designed to be used with high frequencies. It is found here.

[tuv0k]

Thank you for very helpful answer! Is the stackup of nRF51-DK defined in Altium PCB accurate? (imagizer.imageshack.us/.../Cm7w81.png) Would it be necessary to pour GND on the BOTTOM layer?

[Fredrik Sundt Brynhildsvoll]

I am not sure if I understand your first question, but the thickness of the layers is correct and the dielectric properties are too.

Second question: It is not necessary, but good practice. Generally the size of the ground plane is proportional to the performance of the antenna. The bigger the better.

[tuv0k]

Maybe I misunderstand something, but shouldn't the trace between balun and PCB antenna be 50ohm impedance controlled? In that case, distance between top layer and gnd plane matters as well as width of the trace.

[Fredrik Sundt Brynhildsvoll]

I am sorry, I misunderstood your question. Yes you need a ground plane below the matching circuit of the antenna. With a 4 layer pcb it is recommended to use the layer furthest apart from the matching network as a ground plane and keep the inner layers restricted (no ground or lines). This is done on nrf51 dk. I believe you will benefit from looking at this question. You should also see the pcb guidelines for the nrf52 chip.