Causes of small bandwidth of chip antenna

[RalfA]

Hello,

I did my first BLE design and it went wrong  I missed some critical design requirements and I want to ensure that the next prototype performs better. 

The design is a six layer board and the targeted chip antenna was a Johanson 2450AT18D0100 because it's already used in another design as well as the used BalUn. The biggest issues I identified so far:

1) the GND polygons don't have sufficient clearance at one side of the chip antenna (area below the antenna is copper free).

2) the layer below the antenna / 1st inner layer contains multiple power supply polygons, not GND.

3) the whole circuit is surrounded by a RFID antenna PCB trace loop which is GND DC-wise - I think this also affects the BLE antenna.

Obviously, it was hard or even impossible to tune the antenna. So I ordered other chip antennas to check the behaviour depending on orientation, etc For example, I rotated the different antennas on the prototype a few degrees (to get more distance between the antenna and the GND polygons), checked if I can tune it and repeated those steps to get a better understanding.

I was able to tune some of the antennas to 2.44GHz (even the original one depending on orientation) and communication was possible, but it was not stable or the range was low. Comparing the return loss measurement results showed that the (-10dB) bandwidth for any of the used antennas is (much) smaller than the values shown in the antenna datasheets. For example, from the 2450AT18D0100 datasheet the corresponding evaluation board seems to have a -10dB bandwidth of almost 200MHz. My results show 100MHz or less. I assume the small bandwidth is causing unstable or low range communication.

I know that chip antennas have a smaller bandwidth than other antenna types, but it seems that something is additionally reducing the bandwidth on the first prototypes. I want to figure out what is causing the reduced bandwidth before ordering new prototypes.

The new prototypes will use a different component placement ensuring that the BLE antenna is placed at the board edge and the RFID antenna is in the board center. Regarding the chip antenna, the 2450AT18D0100 seems to be suited for center-edge placement which is not possible in this design (here it's more like corner placement), so I maybe have to use a different antenna (I don't know if using this antenna with corner placement will degrade the performance).

The 1st inner layer will be a GND polygon. So, the three issues mentioned above should be covered. Regarding the layer stack, the spacing between the top layer and the 1st inner layer is around 0.1mm, I calculated the needed trace width from BalUn to the antenna as ~0.175mm with a clearance of 0.2mm.

As mentioned, I want to figure out what might have caused the reduced bandwidth, so any hints or thoughts are appreciated.

Regards

[ketiljo]

When you are designing in a chip antenna, the layout, placement and clearance to ground is critical. The cavity in the ground plane around some antennas are part of the design so make sure you follow the datasheet exactly here. 

If the antenna is side mounted, it can't be corner mounted and you have to find another antenna. 

A good ground plane is key for good antenna gain. Use one of the inner planes for ground, first inner plane preferably. Use plenty of vias to connect all ground planes together. 

[RalfA]

Hello ketiljo,

thank you for your answer. 

ketiljo said:

If the antenna is side mounted, it can't be corner mounted and you have to find another antenna. 

Okay, so there's no way to use the 2450AT18D0100.

ketiljo said:

A good ground plane is key for good antenna gain. Use one of the inner planes for ground, first inner plane preferably. Use plenty of vias to connect all ground planes together. 

This is already done in the new layout, especially using the 1st inner layer as GND. Regarding the vias for connecting the layers together, is it enough to use those vias in the area of the BLE circuit/antenna or is it needed to do it on the whole contour of the GND polygons?

Regards

[ketiljo]

RalfA said:

This is already done in the new layout, especially using the 1st inner layer as GND. Regarding the vias for connecting the layers together, is it enough to use those vias in the area of the BLE circuit/antenna or is it needed to do it on the whole contour of the GND polygons?

It depends a bit on the size of the PCB, but a via every 5 to 10 mm in a grid across the whole PCB, plus one at every grounded component will do fine.

[RalfA]

ketiljo said:

It depends a bit on the size of the PCB, but a via every 5 to 10 mm in a grid across the whole PCB, plus one at every grounded component will do fine.

Ah, okay. I used a via spacing of 0.75mm in the BLE area, especially from the BalUn to the tuning network and the antenna. Dedicated vias are also used further away from that area, but not in a grid - will do that.

Regards