How to use the dual core in a application with NRF54L15?

[Mrzhang]

Hi,

Now, I'm doing a project. A device node sends picture data and the other one receives these data. Then the receiver shows the picture on the SSD1306 display.

At receiver's side, there are two threads, one receives the data and the other handle the display. For these two threads' coordination, I use the mailbox. But this would fail if the picture data was sent too fast.

So, I plan to use the other core - RISC-V, to handle the display data. But I know nothing about this dual core application. I just know this may be related to this example, nrf\samples\ipc\ipc_service. But this example doesn't include NRF54L15.

My question is that someone know which example can help me?  Give me as much information as possible. Thank you very much.

[Mrzhang]

Does NRF54L15 support "mbox_data"?

[Priyanka]

Hi,

Yes, you can take a look at the ipc_service sample. This is supported by the nRF54L15 DK:

https://docs.nordicsemi.com/bundle/ncs-latest/page/nrf/samples/ipc/ipc_service/README.html 

"mbox_data" as a concept is supported via the mailbox-based signaling used by the IPC service backends on nRF54L15.

https://docs.nordicsemi.com/bundle/ncs-latest/page/zephyr/services/ipc/ipc_service/backends/ipc_service_icmsg.html 

https://docs.nordicsemi.com/bundle/ncs-latest/page/zephyr/services/ipc/ipc_service/backends/ipc_service_icbmsg.html 

Hope these help.

Regards,

Priyanka

[Mrzhang]

I have tried based on the document above, but it failed to run. Memory error.

I have another question here. 

k_tid_t display_tid = k_thread_create( &display_thread, display_stack, K_THREAD_STACK_SIZEOF(display_stack),

                                           display_thread_entry, ( void* ) context, ( void* ) &pkt_buf, NULL,

                                           DISPLAY_THREAD_PRIORITY, K_INHERIT_PERMS, K_FOREVER );

    k_thread_cpu_mask_clear( display_tid );

    k_thread_cpu_mask_enable( display_tid, 1 );

    k_thread_start( &display_thread )

CONFIG_SCHED_CPU_MASK=y

CONFIG_MP_MAX_NUM_CPUS=2

 

I tried to use this way to let this thread run on the RISC-V core. But the real result was that this thread didn't startup. About this point, do you have any comments?

[Priyanka]

Hi,

PLease take a look at the following documentation:

https://docs.nordicsemi.com/bundle/ncs-latest/page/zephyr/kernel/services/smp/smp.html#cpu_mask 

It's mentioned in the documentation that The functions k_thread_cpu_mask_clear() and k_thread_cpu_mask_enable() are designed to control on which CPUs a thread can run. However, these APIs require that the thread is not currently runnable (i.e., it must be blocked or suspended) when you call them. If you call them on a runnable thread, the function will return an error (-EINVAL) and the operation will not succeed.

Also, the correct usage is to operate on the thread ID (display_tid), not the thread object itself, when starting the thread. Also, ensure that the thread is not started (i.e., is in the K_FOREVER state) before you manipulate the CPU mask.

-Priyanka