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Help, my Project can not exit the GPIO INTERRUPT HANDLER.

bernerd

HI,ALL

my Project can not exit the GPIO INTERRUPT HANDLER.

following is my project.

include "nrf_gpio.h"

include "nrf52.h"

include "boards.h"


define BUTTON_1       13
define LED_1          17

void delay_my(void);
int main(void)
{
	
	nrf_gpio_pin_pull_t config = NRF_GPIO_PIN_PULLUP;
	
	nrf_gpio_pin_sense_t sense = GPIO_PIN_CNF_SENSE_Low;
	

      NRF_GPIOTE->CONFIG[0] = 1<<0          //event
	
	                    |(BUTTON_1 << 8)
	
	                    |(2<<16);        
	
	nrf_gpio_cfg_output(17);

	NRF_GPIOTE->INTENSET = 0x01;
	
	NVIC_SetPriority(GPIOTE_IRQn, 1);
	
       NVIC_ClearPendingIRQ(GPIOTE_IRQn);
	
       NVIC_EnableIRQ(GPIOTE_IRQn);
	
	while(1);
	
	return 0;
	
}




void GPIOTE_IRQHandler(void)

{

	if (NRF_GPIOTE->EVENTS_IN[0] == 1 )

		{

			NRF_GPIOTE->EVENTS_PORT = 0;

			NRF_GPIOTE->TASKS_CLR[0] = 0;

			NRF_GPIOTE->EVENTS_IN[0] = 0;

			nrf_gpio_pin_toggle(LED_1);

		
		}
}
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  • 0

    first of all, why don't you use the definitions provided by nordic?

    second, you don't need to clear any tasks, they just run once when you write 1 to them.

    thirth, in the 'migratinf from nrf51 to nrf52' document is sais the following:

    Interrupt event clearing
Clearing an interrupt event may not take effect immediately.
As CortexRegistered
-M4F has a write buffer on the system bus, write accesses to peripherals/SRAM may be delayed.
In addition, there can be other delays in the bus infrastructure, such as bridges, that may result in writes
occurring after the store instruction has been completed.
To make sure the interrupt line is cleared before exiting an ISR, read back the given event register before
returning. Any read on the system bus will require the write buffer to be emptied first.
Existing code:

    void TIMER0_IRQHandler(void)
    {
     NRF_TIMER0->EVENTS_COMPARE[0] = 0;
    }

Required code:

    void TIMER0_IRQHandler(void)
    {
     NRF_TIMER0->EVENTS_COMPARE[0] = 0;
     (void)NRF_TIMER0->EVENTS_COMPARE[0];
    }
Reply
  • 0

    first of all, why don't you use the definitions provided by nordic?

    second, you don't need to clear any tasks, they just run once when you write 1 to them.

    thirth, in the 'migratinf from nrf51 to nrf52' document is sais the following:

    Interrupt event clearing
Clearing an interrupt event may not take effect immediately.
As CortexRegistered
-M4F has a write buffer on the system bus, write accesses to peripherals/SRAM may be delayed.
In addition, there can be other delays in the bus infrastructure, such as bridges, that may result in writes
occurring after the store instruction has been completed.
To make sure the interrupt line is cleared before exiting an ISR, read back the given event register before
returning. Any read on the system bus will require the write buffer to be emptied first.
Existing code:

    void TIMER0_IRQHandler(void)
    {
     NRF_TIMER0->EVENTS_COMPARE[0] = 0;
    }

Required code:

    void TIMER0_IRQHandler(void)
    {
     NRF_TIMER0->EVENTS_COMPARE[0] = 0;
     (void)NRF_TIMER0->EVENTS_COMPARE[0];
    }
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