NRF54L15, error: 'FLASH_DEVICE_BASE' undeclared, while using BLE for OTA

[varsha@]

Hello,

I am trying to implement OTA through BLE, and as Im building the program, Im getting a build error as : 

error: 'FLASH_DEVICE_BASE' undeclared (first use in this function)
58 | *ret = FLASH_DEVICE_BASE;

The application is getting build properly, but the mcuboot is not getting build.

I am using sdk version v3.0.2.

[varsha@]

Hello, 
I was facing this issue in flash_map_extended.c file in the path : C:\ncs\v3.0.2\bootloader\mcuboot\boot\zephyr\flash_map_extended.c

BOOT_LOG_MODULE_DECLARE(mcuboot);

#if (!defined(CONFIG_XTENSA) && DT_HAS_CHOSEN(zephyr_flash_controller))

#define FLASH_DEVICE_ID SOC_FLASH_0_ID

#define FLASH_DEVICE_BASE CONFIG_FLASH_BASE_ADDRESS

#define FLASH_DEVICE_NODE DT_CHOSEN(zephyr_flash_controller)

#elif (defined(CONFIG_XTENSA) && DT_NODE_EXISTS(DT_INST(0, jedec_spi_nor)))

#define FLASH_DEVICE_ID SPI_FLASH_0_ID

#define FLASH_DEVICE_BASE 0

#define FLASH_DEVICE_NODE DT_INST(0, jedec_spi_nor)

#elif defined(CONFIG_SOC_FAMILY_ESPRESSIF_ESP32)

#define FLASH_DEVICE_ID SPI_FLASH_0_ID

#define FLASH_DEVICE_BASE 0

#define FLASH_DEVICE_NODE DT_CHOSEN(zephyr_flash_controller)

#elif (defined(CONFIG_SOC_SERIES_NRF54HX) && DT_HAS_CHOSEN(zephyr_flash))

#define FLASH_DEVICE_ID SPI_FLASH_0_ID

#define FLASH_DEVICE_BASE CONFIG_FLASH_BASE_ADDRESS

#define FLASH_DEVICE_NODE DT_CHOSEN(zephyr_flash)

#else

#error "FLASH_DEVICE_ID could not be determined"

#endif

static const struct device *flash_dev = DEVICE_DT_GET(FLASH_DEVICE_NODE);

int flash_device_base(uint8_t fd_id, uintptr_t *ret)

{

    if (fd_id != FLASH_DEVICE_ID) {

        BOOT_LOG_ERR("invalid flash ID %d; expected %d",

                     fd_id, FLASH_DEVICE_ID);

        return -EINVAL;

    }

    *ret = FLASH_DEVICE_BASE;

    return 0;

}

In this function, the build error occured when non of the conditions were reached. But when I made the condition as : 

#elif (defined(CONFIG_SOC_SERIES_NRF54HX) || defined(CONFIG_SOC_SERIES_NRF54LX) &&DT_HAS_CHOSEN(zephyr_flash))

The code was build, and OTA also was possible.

Am I supposed to change the libraby file in this way?
Or is there any other workaround for this?

[Einar Thorsrud]

Hi,

You should not need to make any changes in that file. I am curions about how you ended up in this. Are you attempting to enable the BL2 bootloader from TF-M or similar? That is not supported with nRF Connect SDK. Instructions fro adding bootloader in nRF Connect SDK can be found here (I also recomend the module on that here).

[varsha@]

How I added the Bootloader :

mcuboot.overlay - 

/ {

    chosen {

        zephyr,code-partition = &slot0_partition;

        zephyr,flash = &cpuapp_rram;

    };

};

mcuboot.conf:

CONFIG_PM_PARTITION_SIZE_MCUBOOT=0xF000

CONFIG_BOOT_MAX_IMG_SECTORS=512

CONFIG_MPU_ALLOW_FLASH_WRITE=y

CONFIG_FLASH_PAGE_LAYOUT=y

CONFIG_MULTITHREADING=y

CONFIG_FLASH=y

CONFIG_FLASH_MAP=y

sysbuild.conf : 

SB_CONFIG_BOOTLOADER_MCUBOOT=y

prj.conf

CONFIG_IMG_MANAGER=y

CONFIG_STREAM_FLASH=y

CONFIG_BOOTLOADER_MCUBOOT=y

CONFIG_NCS_SAMPLE_MCUMGR_BT_OTA_DFU=y

CONFIG_BOOTLOADER_MCUBOOT=y

[Einar Thorsrud]

Hi,

This looks mostly sensible. However, the .overlay file there have configs you could put in the board files and that are allready there is using a DK. Are you using a DK or a custom board?

If using a DK and to have a working example, you can refer to the smp_svr sample that support the nRF54L15 DK out of the box.

If you don't make any progress, perhaps you can share the full project along with how you build and if using a custom baord, also the custom board files?

[varsha@]

Hello , 

I am using a custom board.

This is the file containing the program. 

[Einar Thorsrud]

Hi,

I suggest referring to the DK board files for reference. Then, you can modify your CT100_v2_nrf54l15_cpuapp.dts to look like this (you may need to make some adjustments tot he memory layout later as I have not considered what may be appropriate in your applicatioon):

/dts-v1/;

#include <nordic/nrf54l15_cpuapp.dtsi>
#include "CT100_v2-pinctrl.dtsi"

/ {
	model = "CT100_v2";
	compatible = "NORDIC,CT100-v2-cpuapp";


	chosen {
		zephyr,code-partition = &slot0_partition;
		zephyr,sram = &cpuapp_sram;
		zephyr,console = &uart20;
		zephyr,shell-uart = &uart20;
		zephyr,uart-mcumgr = &uart20;
		zephyr,bt-mon-uart = &uart20;
		zephyr,bt-c2h-uart = &uart20;
		zephyr,flash-controller = &rram_controller;
		zephyr,flash = &cpuapp_rram;
		zephyr,ieee802154 = &ieee802154;
	};

	leds {
		compatible = "gpio-leds";
		led0: led_0 {
			gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>;
			label = "Green LED 0";
		};
		led1: led_1 {
			gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
			label = "Blue LED 1";
		};
		led2: led_2 {
			gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
			label = "SDA";
		};
		led3: led_3 {
			gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
			label = "SCL";
		};
		led4: led_4 {
			gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
			label = "ACCINT01";
		};
		led5: led5 {
		    gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
    		label = "ADC_enable";
		};

	};

	zephyr,user {
	io-channels = <&adc 1>;
	};

	aliases {
		led0 = &led0;
		led1 = &led1;
		sda  = &led2;
		scl  = &led3;
		accint01 = &led4;
		adcenable = &led5;
		// int_flash = &cpuapp_rram;
	};
};


&gpio1 {
	status = "okay";
};

&gpio2{
	status = "okay";
};
// GNSS Module UART
&uart20 {
	compatible = "nordic,nrf-uarte";
	status = "okay";
	current-speed = <115200>;
	pinctrl-0 = <&uart20_default>;
	pinctrl-1 = <&uart20_sleep>;
	pinctrl-names = "default", "sleep";
};
//LoRa Module UART 
&uart21 {
	compatible = "nordic,nrf-uarte";
	status = "okay";
	current-speed = <9600>;
	pinctrl-0 = <&uart21_default>;
	pinctrl-1 = <&uart21_sleep>;
	pinctrl-names = "default", "sleep";
};


&adc {
	#address-cells = <1>;
	#size-cells = <0>;
	status = "okay";
	channel@1 {
		reg = <1>;
		zephyr,gain = "ADC_GAIN_1_6"; // Divide input voltage by 6
		zephyr,reference = "ADC_REF_INTERNAL"; // Use internal voltage reference (0.6V)
		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>; // Default sample time
		zephyr,input-positive = <NRF_SAADC_AIN7>; /* P1.14 */
		zephyr,resolution = <14>; //12-bit resolution (0 to 4095)
		zephyr,oversampling = <8>;
	};
};

/* FLPR not supported yet, give all SRAM and RRAM to the APP core */
&cpuapp_sram {
	reg = <0x20000000 DT_SIZE_K(256)>;
	ranges = <0x0 0x20000000 DT_SIZE_K(256)>;
};

&gpiote20 {
	status = "okay";
};

&gpiote30 {
	status = "okay";
};

&grtc {
	owned-channels = <0 1 2 3 4 5 6 7 8 9 10 11>;
	/* Channels 7-11 reserved for Zero Latency IRQs, 3-4 for FLPR */
	child-owned-channels = <3 4 7 8 9 10 11>;
	status = "okay";
};


&clock {
    compatible = "nordic,nrf-clock";
    status = "okay";
};

&cpuapp_rram {
	partitions {
		compatible = "fixed-partitions";
		#address-cells = <1>;
		#size-cells = <1>;
		boot_partition: partition@0 {
			label = "mcuboot";
			reg = <0x0 DT_SIZE_K(64)>;
		};
		slot0_partition: partition@10000 {
			label = "image-0";
			reg = <0x10000 DT_SIZE_K(324)>;
		};
		slot0_ns_partition: partition@61000 {
			label = "image-0-nonsecure";
			reg = <0x61000 DT_SIZE_K(324)>;
		};
		slot1_partition: partition@b2000 {
			label = "image-1";
			reg = <0xb2000 DT_SIZE_K(324)>;
		};
		slot1_ns_partition: partition@103000 {
			label = "image-1-nonsecure";
			reg = <0x103000 DT_SIZE_K(324)>;
		};
		/* 32k from 0x154000 to 0x15bfff reserved for TF-M partitions */
		storage_partition: partition@15c000 {
			label = "storage";
			reg = <0x15c000 DT_SIZE_K(36)>;
		};
	};
};

Next, delete the files in your sysbuild folder (particularily the memory layot in the overlay file, as it conflicts with the above). With that, the project builds as expected with the bootloader.

[varsha@]

Hello,

Yes, this worked for me. Thankyou.