NRF54L15, error: 'FLASH_DEVICE_BASE' undeclared, while using BLE for OTA

[varsha@]

Hello,

I am trying to implement OTA through BLE, and as Im building the program, Im getting a build error as : 

error: 'FLASH_DEVICE_BASE' undeclared (first use in this function)
58 | *ret = FLASH_DEVICE_BASE;

The application is getting build properly, but the mcuboot is not getting build.

I am using sdk version v3.0.2.

[varsha@]

Hello , 

I am using a custom board.

This is the file containing the program. 

[Einar Thorsrud]

Hi,

I suggest referring to the DK board files for reference. Then, you can modify your CT100_v2_nrf54l15_cpuapp.dts to look like this (you may need to make some adjustments tot he memory layout later as I have not considered what may be appropriate in your applicatioon):

/dts-v1/;

#include <nordic/nrf54l15_cpuapp.dtsi>
#include "CT100_v2-pinctrl.dtsi"

/ {
	model = "CT100_v2";
	compatible = "NORDIC,CT100-v2-cpuapp";


	chosen {
		zephyr,code-partition = &slot0_partition;
		zephyr,sram = &cpuapp_sram;
		zephyr,console = &uart20;
		zephyr,shell-uart = &uart20;
		zephyr,uart-mcumgr = &uart20;
		zephyr,bt-mon-uart = &uart20;
		zephyr,bt-c2h-uart = &uart20;
		zephyr,flash-controller = &rram_controller;
		zephyr,flash = &cpuapp_rram;
		zephyr,ieee802154 = &ieee802154;
	};

	leds {
		compatible = "gpio-leds";
		led0: led_0 {
			gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>;
			label = "Green LED 0";
		};
		led1: led_1 {
			gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
			label = "Blue LED 1";
		};
		led2: led_2 {
			gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
			label = "SDA";
		};
		led3: led_3 {
			gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
			label = "SCL";
		};
		led4: led_4 {
			gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
			label = "ACCINT01";
		};
		led5: led5 {
		    gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
    		label = "ADC_enable";
		};

	};

	zephyr,user {
	io-channels = <&adc 1>;
	};

	aliases {
		led0 = &led0;
		led1 = &led1;
		sda  = &led2;
		scl  = &led3;
		accint01 = &led4;
		adcenable = &led5;
		// int_flash = &cpuapp_rram;
	};
};


&gpio1 {
	status = "okay";
};

&gpio2{
	status = "okay";
};
// GNSS Module UART
&uart20 {
	compatible = "nordic,nrf-uarte";
	status = "okay";
	current-speed = <115200>;
	pinctrl-0 = <&uart20_default>;
	pinctrl-1 = <&uart20_sleep>;
	pinctrl-names = "default", "sleep";
};
//LoRa Module UART 
&uart21 {
	compatible = "nordic,nrf-uarte";
	status = "okay";
	current-speed = <9600>;
	pinctrl-0 = <&uart21_default>;
	pinctrl-1 = <&uart21_sleep>;
	pinctrl-names = "default", "sleep";
};


&adc {
	#address-cells = <1>;
	#size-cells = <0>;
	status = "okay";
	channel@1 {
		reg = <1>;
		zephyr,gain = "ADC_GAIN_1_6"; // Divide input voltage by 6
		zephyr,reference = "ADC_REF_INTERNAL"; // Use internal voltage reference (0.6V)
		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>; // Default sample time
		zephyr,input-positive = <NRF_SAADC_AIN7>; /* P1.14 */
		zephyr,resolution = <14>; //12-bit resolution (0 to 4095)
		zephyr,oversampling = <8>;
	};
};

/* FLPR not supported yet, give all SRAM and RRAM to the APP core */
&cpuapp_sram {
	reg = <0x20000000 DT_SIZE_K(256)>;
	ranges = <0x0 0x20000000 DT_SIZE_K(256)>;
};

&gpiote20 {
	status = "okay";
};

&gpiote30 {
	status = "okay";
};

&grtc {
	owned-channels = <0 1 2 3 4 5 6 7 8 9 10 11>;
	/* Channels 7-11 reserved for Zero Latency IRQs, 3-4 for FLPR */
	child-owned-channels = <3 4 7 8 9 10 11>;
	status = "okay";
};


&clock {
    compatible = "nordic,nrf-clock";
    status = "okay";
};

&cpuapp_rram {
	partitions {
		compatible = "fixed-partitions";
		#address-cells = <1>;
		#size-cells = <1>;
		boot_partition: partition@0 {
			label = "mcuboot";
			reg = <0x0 DT_SIZE_K(64)>;
		};
		slot0_partition: partition@10000 {
			label = "image-0";
			reg = <0x10000 DT_SIZE_K(324)>;
		};
		slot0_ns_partition: partition@61000 {
			label = "image-0-nonsecure";
			reg = <0x61000 DT_SIZE_K(324)>;
		};
		slot1_partition: partition@b2000 {
			label = "image-1";
			reg = <0xb2000 DT_SIZE_K(324)>;
		};
		slot1_ns_partition: partition@103000 {
			label = "image-1-nonsecure";
			reg = <0x103000 DT_SIZE_K(324)>;
		};
		/* 32k from 0x154000 to 0x15bfff reserved for TF-M partitions */
		storage_partition: partition@15c000 {
			label = "storage";
			reg = <0x15c000 DT_SIZE_K(36)>;
		};
	};
};

Next, delete the files in your sysbuild folder (particularily the memory layot in the overlay file, as it conflicts with the above). With that, the project builds as expected with the bootloader.

[varsha@]

Hello,

Yes, this worked for me. Thankyou.