Cannot get UART00 to function

Question

SDK v3.0.2 Toolchain 3.01

I'm beating my head against the wall for what should be a trivial matter. I need to use P2 for uart: RX is P2.00 TX is P2.02. No RTS CTS in use.

Originally this was on a custom PCB, but to test I've switched to my 54L15DK. (I have cut/bridged the relevant DK jumpers to use the P2 pins for I/O.) For testing I'm using a slightly modified "Hello World" sample. I'm using a scope to monitor the pins, they just go high and stay high.

I'm sure this is a DTS problem and probably flow control related. But none of the DKs use UART00 so I can't cross reference...

Here is my DTS

/dts-v1/;
#include <nordic/nrf54l15_cpuapp.dtsi>
#include "test-pinctrl.dtsi"

/ {
	model = "UART test";
	compatible = "MyCo,test-cpuapp";

	chosen {
		zephyr,console = &uart00;
		zephyr,code-partition = &slot0_partition;
		zephyr,sram = &cpuapp_sram;
		zephyr,flash-controller = &rram_controller;
		zephyr,flash = &cpuapp_rram;
		zephyr,ieee802154 = &ieee802154;
	};

	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
	};
};

&cpuapp_sram {
	status = "okay";
};

&grtc {
	owned-channels = <0 1 2 3 4 5 6 7 8 9 10 11>;
	/* Channels 7-11 reserved for Zero Latency IRQs, 3-4 for FLPR */
	child-owned-channels = <3 4 7 8 9 10 11>;
	status = "okay";
};

&cpuapp_rram {
	partitions {
		compatible = "fixed-partitions";
		#address-cells = <1>;
		#size-cells = <1>;
		boot_partition: partition@0 {
			label = "mcuboot";
			reg = <0x0 DT_SIZE_K(64)>;
		};
		slot0_partition: partition@10000 {
			label = "image-0";
			reg = <0x10000 DT_SIZE_K(324)>;
		};
		slot0_ns_partition: partition@61000 {
			label = "image-0-nonsecure";
			reg = <0x61000 DT_SIZE_K(324)>;
		};
		slot1_partition: partition@b2000 {
			label = "image-1";
			reg = <0xb2000 DT_SIZE_K(324)>;
		};
		slot1_ns_partition: partition@103000 {
			label = "image-1-nonsecure";
			reg = <0x103000 DT_SIZE_K(324)>;
		};
		/* 32k from 0x154000 to 0x15bfff reserved for TF-M partitions */
		storage_partition: partition@15c000 {
			label = "storage";
			reg = <0x15c000 DT_SIZE_K(36)>;
		};
	};
};

&clock {
	status = "okay";
};

&i2c20{
	status = "okay";
  compatible="nordic,nrf-twim";
	pinctrl-0 = <&i2c20_default>;
  pinctrl-1 = <&i2c20_sleep>;
	pinctrl-names = "default", "sleep";
	wakeup-source;
};

&i2c30{
	status = "okay";
  compatible="nordic,nrf-twim";
	pinctrl-0 = <&i2c30_default>;
  pinctrl-1 = <&i2c30_sleep>;
	pinctrl-names = "default", "sleep";
	wakeup-source;
};

&gpio1 {
	status = "okay";
};

&gpio2 {
	status = "okay";
};

&gpiote20 {
    status = "okay";
};

&regulators {
	status = "okay";
};

&vregmain {
	status = "okay";
	regulator-initial-mode = <NRF5X_REG_MODE_DCDC>;
};

&uart00 {
	status = "okay";
  current-speed = <115200>;
  pinctrl-0 = <&uart00_default>;
  pinctrl-1 = <&uart00_sleep>;
  pinctrl-names = "default", "sleep";
};

&spi00 {
  status = "disabled";
};
 
 
&uicr {
	nfct-pins-as-gpios;
};

and DTSI

&pinctrl {

	uart00_default: uart00_default {
		group1 {
			psels = <NRF_PSEL(UART_TX, 2, 2)>;
		};
		group2 {
			psels = <NRF_PSEL(UART_RX, 2, 0)>;
			bias-pull-up;
		};
	};

	uart00_sleep: uart00_sleep {
		group1 {
			psels = <NRF_PSEL(UART_TX, 2, 2)>;
			low-power-enable;
		};
	};

	/omit-if-no-ref/ uart30_default: uart30_default {
		group1 {
			psels = <NRF_PSEL(UART_TX, 0, 0)>,
				<NRF_PSEL(UART_RTS, 0, 2)>;
		};
		group2 {
			psels = <NRF_PSEL(UART_RX, 0, 1)>,
				<NRF_PSEL(UART_CTS, 0, 3)>;
			bias-pull-up;
		};
	};

	/omit-if-no-ref/ uart30_sleep: uart30_sleep {
		group1 {
			psels = <NRF_PSEL(UART_TX, 0, 0)>,
				<NRF_PSEL(UART_RX, 0, 1)>,
				<NRF_PSEL(UART_RTS, 0, 2)>,
				<NRF_PSEL(UART_CTS, 0, 3)>;
			low-power-enable;
		};
	};


	/omit-if-no-ref/ pwm20_default: pwm20_default {
		group1 {
			psels = <NRF_PSEL(PWM_OUT0, 1, 10)>;
		};
	};

	/omit-if-no-ref/ pwm20_sleep: pwm20_sleep {
		group1 {
			psels = <NRF_PSEL(PWM_OUT0, 1, 10)>;
			low-power-enable;
		};
	};

	/omit-if-no-ref/ grtc_default: grtc_default {
		group1 {
			psels = <NRF_PSEL(GRTC_CLKOUT_FAST, 1, 8)>,
				<NRF_PSEL(GRTC_CLKOUT_32K, 0, 4)>;
		};
	};

	/omit-if-no-ref/ grtc_sleep: grtc_sleep {
		group1 {
			psels = <NRF_PSEL(GRTC_CLKOUT_FAST, 1, 8)>,
				<NRF_PSEL(GRTC_CLKOUT_32K, 0, 4)>;
			low-power-enable;
		};
	};

	i2c20_default: i2c20_default {
		group1 {
			psels = <NRF_PSEL(TWIM_SCL, 1, 12)>, <NRF_PSEL(TWIM_SDA, 1, 13)>;
		};
	};

	i2c20_sleep: i2c20_sleep {
		group1 {
			psels = <NRF_PSEL(TWIM_SCL, 1, 12)>, <NRF_PSEL(TWIM_SDA, 1, 13)>;
      low-power-enable;
		};
	};

	i2c30_default: i2c30_default {
		group1 {
			psels = <NRF_PSEL(TWIM_SCL, 1, 12)>, <NRF_PSEL(TWIM_SDA, 0, 2)>;
		};
	};

	i2c30_sleep: i2c30_sleep {
		group1 {
			psels = <NRF_PSEL(TWIM_SCL, 1, 12)>, <NRF_PSEL(TWIM_SDA, 0, 3)>;
      low-power-enable;
		};
	};


};



&lfxo {
	load-capacitors = "internal";
	load-capacitance-femtofarad = <15500>;
};

&hfxo {
	load-capacitors = "internal";
	load-capacitance-femtofarad = <15000>;
};

prj.conf

CONFIG_CONSOLE=y
CONFIG_SERIAL=y

and finally the code

#include <stdio.h>
#include <zephyr/kernel.h>

int main()
{
	while(true)
	{
		printf("Hello World! %s\n", CONFIG_BOARD_TARGET);
		k_sleep(K_MSEC(500));
	}
	return 0;
}

Nick_RA · Accepted Answer

It turned out to be something painfully stupid... 
 I tried a fresh build using the 54L15DK, with my DTS as an overlay and it worked. So I checked the generated files as you suggested and found.... CONFIG_UART_CONSOLE=n 
 It's set in my project and obviously in the DK config, but was missing because I switched to using the simple hello_world sample to get the hardware and DTS working. I can't quite see why it should be needed anyway as the "chosen" property tells Zephyr to use the uart for console, but there you go. 
 Anyway it's working now, thanks for your help.

Cannot get UART00 to function

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