Hello,
Are you sure this is not due to differences in clock between peers in the system, and what you experience is due to buffer underrun or overrun?
Kenneth
First of all, none of these are the root cause. The STM32 chip has been widely and maturely used in our other systems, with a large shipment volume from the company. There are no issues with data acquisition or SPIM transmission on the STM32 side.
The clock for the nRF5340's SPIS is derived from the SPIM. Furthermore, I have also conducted a test where the STM32 sends a single 20-byte data packet every 60 milliseconds. In this scenario, the nRF5340's SPIS still exhibits a phenomenon where one data packet is received slowly per second—it takes 90 milliseconds to receive that specific packet, while the average reception time is 60 milliseconds.
Currently, my suspicion is whether the system has enabled the default configuration of the nRF5340 entering sleep mode every second, which thereby affects the functionality of the SPIS.
Not sure I quite understand, normally as an SPI master you just pass the 20byte, how do you observe that the nRF5340 sometimes use 90ms instead of 60ms to receive the data? Are you using some handshaking of some sort, is the delay before or after the SPI master try to write the data?
Kenneth
I use the log version, which prints timestamps. The SPI master sends a packet at 60ms intervals, and I calculate the interval difference between consecutive packets received by the SPI slave. Additionally, the first two bytes of each packet contain a counter, allowing me to check for any packet loss.
I suggest to connect some kind of logic analyzer, it's still not clear to me. I don't understand how an SPI slave can delay an SPI master, unless there is some handshaking.
Do you have any delay between CSN go low and first byte on the SPI master? e.g. 10us.
Kenneth
I suggest to connect some kind of logic analyzer, it's still not clear to me. I don't understand how an SPI slave can delay an SPI master, unless there is some handshaking.
Do you have any delay between CSN go low and first byte on the SPI master? e.g. 10us.
Kenneth