Documentation contradiction in LATCH register clearing description (Page 323, nRF52840 PS v1.11)

[Harrisonhall]

In the nRF52840 Product Specification PDF v1.11, on page 323, the third paragraph down states:

1. "If the CPU performs a clear operation on a bit in the LATCH register when the associated PINx.DETECT signal is high, the bit in the LATCH register will not be cleared."

2. "The LATCH register will only be cleared if the CPU explicitly clears it by writing a 1 to the bit that shall be cleared"

This is contradictory. A "clear operation" IS writing a 1 to the bit. In the LATCH register definition, on page 346, it clearly states "Write '1' to clear" - so a "clear operation" IS writing a 1 to the bit.

Therefor, the first and second sentence contradict each other.

Suggested correction:

"Writing 1 to clear a LATCH bit will only succeed if the pin is no longer matching its SENSE condition. If the pin is still matching its SENSE condition, the bit will remain set."

References:

https://docs-be.nordicsemi.com/bundle/ps_nrf52840/attach/nRF52840_PS_v1.11.pdf?_LANG=enus

[Priyanka]

Hi,

I don't think the documentation is contradictory. What I understood from the docs is that, say, PIN0.DETECT is high, then the 0 bit in the LATCH register goes high. After that, even if CPU writes 1 in order to clear the LATCH register's 0 bit, this will actually be done only if the PIN0.DETECT goes low and then the CPU writes 1 to the LATCH register.
As long as these two conditions (PIN0.DETECT should go low & CPU then writes 1 to the LATCH register) are not met, the 0 bit in the LATCH register is not cleared.

Nevertheless, I have inquired internally in order to verify this and will get back to you.

-Priyanka