Hello Nordic
We're developing an application where the second firmware partition is saved in external storage, which we would like to be accessible by both MCUboot and the main application.
Our custom board using an NRF54L15 SOC combined with a w25q16jvsniq NOR flash uses the SQSPI firmware to communicate with this external flash.
This works great when our application is running without MCUBoot, as well as whilst MCUboot is using it to check our external storage for a valid image, but when MCUboot jumps to our first image slot things go wrong.
The main application is stuck in the following code snippet from nrf_sqspi.c:
while (nrf_qspi2_enable_check(p_qspi->p_reg) != false)
{
// Wait for peripheral to becore ready to receive communication.
}
We can resolve this by adding the following line to the init function in the same file, after which the application gets loaded correctly:
nrfx_err_t nrf_sqspi_init(const nrf_sqspi_t * p_qspi, const nrf_sqspi_cfg_t * p_config)
{
NRFX_ASSERT(p_qspi);
NRFX_ASSERT(p_config);
// Adding this resolves the issue
nrf_vpr_cpurun_set(NRF_VPR, false);
...
//rest of code
}
Our question is the following:
Does the sqspi peripheral incorrectly initialize after MCUboot, or are we missing some kind of configuration?
Perhaps it is the responsibility of MCUboot to correctly deinit SQSPI before jumping to the current application slot.
In case this is a bug: Is our approach acceptable to circumvent the issue, and if not: What is?
Some references:
Nrf Connect SDK v3.1.0
sqspi firmware v1.1.0
partitions.yml:
+-------------------------------+ | 0xffd080: bootconf (0x4 - 4B) | +-------------------------------+ external_flash (0x200000 - 2048kB): +------------------------------------------------+ | 0x0: littlefs_storage (0x50000 - 320kB) | | 0x50000: mcuboot_secondary (0x143000 - 1292kB) | | 0x193000: external_flash (0x6d000 - 436kB) | +------------------------------------------------+ flash_primary (0x165000 - 1428kB): +----------------------------------------------------+ | 0x0: mcuboot (0x20000 - 128kB) | +---0x20000: mcuboot_primary (0x143000 - 1292kB)-----+ | 0x20000: mcuboot_pad (0x800 - 2kB) | +---0x20800: mcuboot_primary_app (0x142800 - 1290kB)-+ | 0x20800: app (0x142800 - 1290kB) | +----------------------------------------------------+ | 0x163000: settings_storage (0x2000 - 8kB) | +----------------------------------------------------+ otp (0x4fc - 1kB): +-----------------------------+ | 0xffd500: otp (0x4fc - 1kB) | +-----------------------------+ sram_primary (0x2ec00 - 187kB): +--------------------------------------------+ | 0x20000000: sram_primary (0x2ec00 - 187kB) | +--------------------------------------------+
Some relevant config:
softperipheral_ram: memory@2003c000 {
reg = <0x2003c000 0x4000>;
ranges = <0 0x2003c000 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
sqspi: sqspi@3b40 {
compatible = "nordic,nrf-sqspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3b40 0x200>;
status = "okay";
zephyr,pm-device-runtime-auto;
};
};
&sqspi {
compatible = "nordic,nrf-sqspi";
status = "okay";
w25q16: w25q16jvsniq@0 {
status = "okay";
compatible = "jedec,mspi-nor";
reg = <0>;
jedec-id = [ef 40 15];
size = <DT_SIZE_M(16)>;
has-dpd;
t-enter-dpd = <3000>;
t-exit-dpd = <30000>;
sfdp-bfp = [
e5 20 f1 ff ff ff ff 03 44 eb 08 6b 08 3b 04 bb
ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52
10 d8 00 ff 23 72 f5 00 82 ed 04 cc 44 83 68 44
30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff
];
mspi-max-frequency = <DT_FREQ_M(16)>;
mspi-io-mode = "MSPI_IO_MODE_QUAD_1_1_4";
mspi-data-rate = "MSPI_DATA_RATE_SINGLE";
mspi-hardware-ce-num = <1>;
mspi-cpp-mode = "MSPI_CPP_MODE_0";
mspi-endian = "MSPI_BIG_ENDIAN";
mspi-ce-polarity = "MSPI_CE_ACTIVE_LOW";
#address-cells = <1>; // Address is 1 cell (32-bit)
#size-cells = <1>; // Size is 1 cell (32-bit)
};
};
Thanks in advance
Jeroen
