Seeking confirmation about Bluetooth's Danger Zone

[Grungagrs26]

Hello, 

I am at the very, very early stages of my project, doesn't it even a name yet. Right now I am thinking of using nrf52840 for a Bluetooth operation while being supplied by a tl5955 battery.

Before committing to the nrf52840, I decided to read the posts here about possible problems and malfunctions, with or without Bluetooth. 

One of these problems caught my interest. There seems to be many situations where a nrf52840 experiences reboots while current bursts are happening, common in Bluetooth Tx.

While it's obvious that weak batteries or with high internal resistance will produce such events , one common thread is that these events seem to happen at a higher frequency when the voltage supply is at a 2.6 V - 3.0V range. 

Is this a known or common "danger zone" ?  Because the battery I am planning to use starts at 3.6V and is considered functional until it reaches 2.0V.

If this zone truly exists , I will have to use another device or change the battery. 

Can someone help with this? 

[Ressa]

Hi,

Thanks for contacting us.
Regarding the issue you mentioned, it is more related to the external power supply or poor decupling consideration and layout rather than the nRF52840 itself. As you mentioned during situations like BLE transmission with high TX power, the current consumption can go higher for a short period of time and if the external circuitry (battery or decupling capacitors) is not able to supply the high current reliably, then there will be voltage drops in supply lines and if these voltage drops go below the brownout reset (BOR) threshold (1.6V in system On), then you will experience reboots, and this behavior will be more visible when your battery voltage is in lower range. So I would say make sure the battery has low internal resistance and is able to supply the peak currents during BLE transmission, also make sure to use enough bulk capacitors with different values next to the supply pins of nRF52840. Following closely the reference schematic and layout would mitigate most of these issues. You can also use PMICs to ensure more reliable power supply to the SoC.

Best regards;
Ressa

[Grungagrs26]

Is there some sort of reference material or experimental data regarding mitigating this phenomenon that I could be looking up? 

[Ressa]

Hi,

Following the refence design schematic and layout and considering the power supply limitation in the design, would mitigate the concern entirely. There is no official data regarding the phenomenon and that can happen to any SoC with not good enough circuitry/layout design. 

Best regards,
Ressa