Why Is There a Long Delay for CS Pull-High After SPI Data Exchange? (Need to Shorten It)

We are not using the NRF5340DK board. According to tests, after initiating an SPI data exchange, the program is delayed in executing the next CS pull-high operation, resulting in excessively long execution time for the entire SPI command. However, the SPI clock line ends within a very short period. I would like to know what operations are being executed between the end of the SPI clock line and the chip's response to my CS pull-high operation, and whether I can shorten this time as much as possible.

Parents Reply Children
No Data
Related