nRF5340 I2C driving strength tuning

[Poki Huang]

Hi

We measure I2C SCL falling time is  5.87ns, little faster than spec. 6.54ns (20*1.8/5.5)

We use PIN_CNF[n] (Address offset: 0x200 + (n × 0x4)) ID D drive to tune, but it only have standard and high drive, the default is standard, we tune to high drive and falling time become faster

So except PIN_CNF[n], any other register we can use to tune drive strength?

Thank you

Poki

[Kenneth]

Hello,

Some pins also have extra high drive, ref: https://docs.nordicsemi.com/bundle/ps_nrf5340/page/chapters/pin.html 

Kenneth

[Poki Huang]

Hi Kenneth:

Sorry for confuse

I mean I2C SCL falling time is  5.87ns, little shorter than spec. 6.54ns (20*1.8/5.5)

This measurement is by standard drive setting, and high drive setting will cause the falling time shorter, but I need this timing longer than 6.54ns, not use more stronger drive like extra high drive

So I want to know if any other register can tune I2C SCL drive more weak to let SCL falling longer

Thank you

Poki

[Kenneth]

Usually using smaller pull up resistors or add some capacitance can do the trick. Though I was not aware there was also a requirement that fall times must be larger than a minimum value, I was only aware there were some max values that is must be lower than.

Kenneth