nPM1300 I2C SCL Tf & Tlow timing

[Poki Huang]

Hi 

According I2C standard, there is a requirement regarding falling speed of SCL/SDA which is > 20*1.8/5.5=6.54ns, and our measurement result of Tf on SCL is 5.732ns.

I didn’t see this Tf requirement in datasheet of nPM1300

Do you think we can waive this Tf requirement for nPM1300?

Also Tlow spec. is >1.3us, and our measurement result of Tlow is 1.237us.

I didn’t see this Tlow requirement in datasheet of nPM1300

Do you think we can waive this Tlow requirement for nPM1300?

Thank you

Poki

[Ressa]

Hi Poki,

Regarding your measurements , please note that fall time and rise time of digital signals including I2C signals depend on the total capacitance on the line and also resistor values for pull up, so please make sure to take into account these parameters while measuring.  For example increased line capacitance will cause slower rise/fall. These physical parameters are usually the dominant factor rather than the chip itself. Also please consider the data rate used in the signaling and make sure you are comparing the spec for exact same signaling speed and Mode. Regarding nPM1300, general recommendation is to closely follow reference design schematic and layout which is used for product validation. 
Recommended reading

Best regards,
Ressa

[Poki Huang]

Hi Ressa:

Thanks feedback, our frequency is 400KHz within spec. 100KHz~1000KHz

And I know those you mention can affect rise/fall time

I just want to know since Tf & Tlow of SCL spec. is not mentioned at nPM1300 datasheet

Can we wave this two items?

Or should we follow I2C standard, Tf need larger than 20*1.8/5.5=6.54ns, Tlow need larger than 1.3us?

Thank you

Poki

I2C standard

[Ressa]

Hi Poki,

I agree that according to your measurements it is slightly out of spec (less than 10 %), but would you please let me know how was your measurement procedure? I mean for Tlow did you consider the absolute 0 level duration as low time ? According to the spec , Tlow is the time the signal is below 0.3*VDD. 

[Poki Huang]

Hi Ressa:

Yes for Tlow we measure below 0.3*VDD timing, and Tf from 0.7*VDD to 0.3*VDD timing

Pic. as below

Tlow

Tf

[Ressa]

Hi Poki,

Thanks for sharing the details. I still think it is not good idea to check the extreme example as we are choosing max speed at fast mode and checking minimum low time. Also considering the clock accuracy and other uncertainties, less than 10 % is not bad and if you don't see any problem with communication over a few hardware samples then no need to worry about that. Also another thing is to measure the accuracy of I2C clock or lets say actual data rate. For example if it is slightly higher than 400 kbps then it will directly translate into shorter "low time".