[SAADC] Sampling Modes and Power Consumption Trade-offs

Hello,

I have seen many topics regarding the SAADC sampling modes and power consumption trade-offs on DevZone, but none of them clearly address my concerns. I would like to ask a couple of questions that could ultimately serve as a guideline for choosing the optimal SAADC sampling method depending on the use case.

1. Continuous Sampling (No CPU, Hardware Only)

For continuous sampling, we have two options. We can control the sampling using either a Task or a Timer.

The Timer is derived from the PCLK16M (HFCLK controller) and supports a limited frequency range of <7816, 200000> Hz (SAADC).
The Task can be used with the PPI peripheral in combination with the Timer peripheral, requesting PCLK1M from the HFCLK controller (SAADC + PPI + TIMER).
The Task approach allows lower frequencies below 7816 Hz and multi-channel sampling with no CPU intervention until the provided buffer is full.

Continuous sampling can be implemented using either a single-buffer or double-buffer approach.
However, with this method, EasyDMA remains enabled between each sample taken. EasyDMA has a significant impact on overall power consumption during sampling, which is why the sampling frequency doesn't matter much. Typical current consumption is approximately 1.24mA, as stated in the datasheet.

Is all of that true? Are there any methods to run Continuous Sampling without bothering the CPU?

2. One-Shot Sampling

To eliminate the substantial current consumption impact of EasyDMA, one-shot sampling must be used. In this method, sampling occurs in software, meaning the SAADC ISR handler is executed for each sample taken. This also implies that a fixed sampling rate can no longer be guaranteed because the CPU may need to process other tasks, which can delay the execution of the SAADC ISR handler. For "fixed-rate wannabe" sampling, the RTC CC interrupt should be used, as the TIMER can increase current consumption to a level where continuous sampling might ultimately be the better choice.

In the context of Zephyr, is there any difference between utilizing the kernel timer API (k_timer_start()) for such a case versus running one-shot measurements in the RTC CC interrupt handler, knowing that the Zephyr system clock utilizes the RTC? Which approach is considered better for providing fixed-rate one-shot sampling?

Is it possible to delegate one-shot sampling to hardware by using PPI + RTC, like this:

In other words, is there a way to achieve fixed-rate sampling controlled by hardware without EasyDMA, where each sampling sequence is a one-shot operation (START, SAMPLE, STOP) and the interrupt is raised only after collecting X samples?

PPI channel start: Event = NRF_RTC_EVENT_COMPARE_1, Task = NRF_SAADC_TASK_START

PPI channel sample: Event = NRF_SAADC_EVENT_STARTED, Task = NRF_SAADC_TASK_SAMPLE

PPI channel stop: Event = NRF_SAADC_EVENT_END, Task = NRF_SAADC_TASK_STOP

Thanks in advance! 

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  • Hi,

    Is all of that true?

    Yes.

    Are there any methods to run Continuous Sampling without bothering the CPU?

    Not any other methods than the ones mentioned.


    Is it possible to delegate one-shot sampling to hardware by using PPI + RTC, like this:

    In other words, is there a way to achieve fixed-rate sampling controlled by hardware without EasyDMA, where each sampling sequence is a one-shot operation (START, SAMPLE, STOP) and the interrupt is raised only after collecting X samples?

    No, with this approach, the new sample will overwrite the last sample every time it is triggered. There is no auto-increment in the buffer pointer in the SAADC after it is stropped, so the CPU is required to update the buffer pointer before each triggering of the START task.


    Regards,
    Jonathan

Reply
  • Hi,

    Is all of that true?

    Yes.

    Are there any methods to run Continuous Sampling without bothering the CPU?

    Not any other methods than the ones mentioned.


    Is it possible to delegate one-shot sampling to hardware by using PPI + RTC, like this:

    In other words, is there a way to achieve fixed-rate sampling controlled by hardware without EasyDMA, where each sampling sequence is a one-shot operation (START, SAMPLE, STOP) and the interrupt is raised only after collecting X samples?

    No, with this approach, the new sample will overwrite the last sample every time it is triggered. There is no auto-increment in the buffer pointer in the SAADC after it is stropped, so the CPU is required to update the buffer pointer before each triggering of the START task.


    Regards,
    Jonathan

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