Hi,
I'm building an non-secure application for nrf15l15 SoC using NCS SDK v3.0.2. The available SRAM memory for my application is set to 188K in the base dtsi files ( see dump below ) instead of 256K that is available on the SOC. I checked that the final .dts generated for my application has cpu_sram set to 188K. It looks like we are reserving 68K for FLPR which doesn't get used for my application.
My question is , if I'm not using FLPR , can I safely override cpuapp_sram to 256K in my overlay file. My application is not fitting within 188K limits ( TF-M also gobbles up about 55K ) and I'd like to explore all options before going down the route of optimizing the application.
cpu_flpr_sram node anyway gets deleted as shown below ( my final dts also doesn't have it ) - so it looks like we are just letting go of 68K worth of SRAM without any use. I'd happily take that and use it for my application. I'd like to be sure that this is okay and doesn't cause any other issues. Please clarify.
DUMPS
From zephyr/dts/common/nordic/nrf54l15.dtsi
&cpuapp_sram {
/delete-node/ &cpuflpr;
/delete-node/ &cpuflpr_rram;
/delete-node/ &cpuflpr_sram;
/delete-node/ &cpuflpr_clic;
