1、About SPI（P1） CS active but clk delay 7us comed late ,and clk is overd（data tx is over） but CS delay 40uS active. 2、About SPI（P2） CS active but clk delay 5us comed late ,and clk is overd（data tx is over） but CS delay 12uS active.

[Lzs]

Hello：

      How to reduce this time.

[Turbo J]

Please reformat, this is not readable. This may also need a plot from a scope or logic analyzer.