NRF54L15 SPIS needs CONSTLAT

[Bruno Randolf]

I just wanted to notify that I need to set CONFIG_SOC_NRF_FORCE_CONSTLAT=y in order for a NRF54L15 to be able to respond as a SPI slave (SPIS) using nrfx SPIS code.

Otherwise it only works when a JLink debugger is connected, but otherwise not, after it has been rebooted for example and the debugger is physically connected, but not "active"...

My configuration uses SPIS20 and GPIO pins from port 1, so as far as I understand it's not cross-domain?

I am noting this mostly for other people who might get into a similar situation. Also I'm curious to hear if there is an explanation why this is necessary? 

[Kenneth]

Hello,

I can't think of anything in specific, but one difference when using constlat is the wakeup time, so in constlat you can likely have very short time between CS low and first clock edge, while in normal low power mode, the timing must be higher to ensure the nRF54L15 can startup the regulators and open easydma channel between the spis peripheral and ram buffer internally, so maybe try with 10us (or more) between CS low and first clock edge just to check if that may be part of the problem?

Just to rule out a few things,
- which version of the nRF54L15DK do you have?
- which ncs or ncs bare metal are you using?
- do you see problems if using the zephyr spis driver test sample? 
\zephyr\tests\drivers\spi\spi_controller_peripheral\boards\nrf54l15dk_nrf54l15_cpuapp.overlay (it use spis21, so similar)

For anyone else finding this page, what is important to check for these kind of problems is that you have followed:
https://docs.nordicsemi.com/bundle/ps_nrf54L15/page/spis.html#d1504e788 
https://docs.nordicsemi.com/bundle/ps_nrf54L15/page/chapters/pin.html#ariaid-title2 
https://docs.nordicsemi.com/bundle/ps_nrf54L15/page/chapters/pin.html#d380e188 

Kenneth

[Bruno Randolf]

First off, I would like to say that enabling CONSTLAT is not a problem in my use case, since we are not battery powered. But I am happy to find out more about the situation.

Your comment about the response time is correct: if i change the code on the master (ESP) side to toggle CS manually by GPIO, before and after the SPI transaction, then it already works, i don't even need to add a delay. I use the build-in CS management normally, which seems to be too fast. Unfortunately I don't have the tools right now to trace the SPI bus to see the difference in timing.

I am using my own custom board which has a NRF54L15 connected to an ESP32-C5 (spi master).

I am using NCS v3.2.1.

I have complied and flashed the test case to a NRF54L15DK but don't know how to see if it works or not.

[Kenneth]

Bruno Randolf said:

Your comment about the response time is correct: if i change the code on the master (ESP) side to toggle CS manually by GPIO, before and after the SPI transaction, then it already works, i don't even need to add a delay.

Sounds good, then root cause is that you need to have a delay between CS low and first clock when waking up from low power idle state.

Kenneth