Floating GPIO configuration

[Adam Broders]

Hello,

We have a dual-purpose connection in our design where the signal can be either an analog input or a digital output. We have done some testing and can see that we can switch between the two functions to get the desired affect, but it complicates a few aspects of FW. We are considering connecting two connections: the analog connection and a GPIO.

Is there a GPIO state (perhaps input, buffer disconnected) where the GPIO interface tolerates mid-rail voltages, is "very high" high impedance (10Mohm or is at least known to calibrate the math), and is easy to reconfigure as an output?

Thanks!

[hmolesworth]

"Input buffer disconnect" mode may well do what you require, but I would argue that it would be better to test this on the specific nRF as there is no clear description of where the disconnect is internally physically placed. There is a vanishingly small window somewhere near VDD/2 where slow or floating input feedthrough leakage may occur; this is not leakage into or out of the io pin but instead leakage through internal FETs from internal VDD to internal GND caused by high and low FETs being slightly biased on by an input voltage falling within that window. If input disconnect mode isolates all such FETs then maybe there is no issue, but I don't see this guaranteed.

More info here; all semi manufacturers discuss this, this is TI: scba004e.pdf