Floating GPIO configuration

[Adam Broders]

Hello,

We have a dual-purpose connection in our design where the signal can be either an analog input or a digital output. We have done some testing and can see that we can switch between the two functions to get the desired affect, but it complicates a few aspects of FW. We are considering connecting two connections: the analog connection and a GPIO.

Is there a GPIO state (perhaps input, buffer disconnected) where the GPIO interface tolerates mid-rail voltages, is "very high" high impedance (10Mohm or is at least known to calibrate the math), and is easy to reconfigure as an output?

Thanks!

[Szabolcs]

You can see the GPIO block diagram in the nRF54LM20A datasheet:

Here, you can see that there is a switch before the input buffer stage, hence the name "Input buffer disconnect". In this mode, the buffer stage is actually isolated from the GPIO pin. So in this mode, the issue you mentioned is not relevant.

Unfortunately, we don't have more detailed information on these switches, but they can be assumed to be "almost-ideal" analog switches.

If you need to have a pin with very specific characteristic, you could use a tri-state buffer or line driver (for example something from the 74xx series).

[hmolesworth]

I agree with your comments on the drawing, however it is not strictly accurate in the case of the nRF52 series - I haven't checked the nRF54 yet. I say this as the input pullup/pulldown is shown downwind of the input disconnect but even when the disconnect (nRF52) is open the pullup/pulldown still affects the pin; I have tested this. If the pullup/pulldown is always connected to the pin, then an input FET hi/lo might also always be connected prior to the input disconnect circuit.

Here are some older results on the nRF52832, with input disconnect and nothing connected to all 32 io pins the current increases to 6.47mA when driving low with pullup enabled and similar when driving high with pulldown enabled.

All 32 io pins have no external connections; all 32 pins driven identically

 PPK     Measured
 ======  ========
 1.66uA  2.971V with errata workarounds, no i/o
 1.51uA  2.985V no errata workarounds, no i/o
 1.49uA  2.989V (PIN_OUTPUT | DISCONNECT | PULLNONE | FORCE_S0S1 | SENSE_OFF) Drive Low
 1.49uA  2.999V (PIN_OUTPUT | DISCONNECT | PULLDOWN | FORCE_S0S1 | SENSE_OFF) Drive Low
 6.47mA  2.894V (PIN_OUTPUT | DISCONNECT | PULLUP   | FORCE_S0S1 | SENSE_OFF) Drive Low
 6.47mA  2.889V (PIN_OUTPUT | CONNECT    | PULLUP   | FORCE_S0S1 | SENSE_OFF) Drive Low

 1.51uA  2.959V (PIN_OUTPUT | DISCONNECT | PULLNONE | FORCE_S0S1 | SENSE_OFF) Drive High
 6.42mA  2.877V (PIN_OUTPUT | DISCONNECT | PULLDOWN | FORCE_S0S1 | SENSE_OFF) Drive High
 1.53uA  2.938V (PIN_OUTPUT | DISCONNECT | PULLUP   | FORCE_S0S1 | SENSE_OFF) Drive High
 6.47uA  2.889V (PIN_OUTPUT | CONNECT    | PULLUP   | FORCE_S0S1 | SENSE_OFF) Drive High

The nRF54 may behave differently, but the datasheet schematic looks similar so my suggestion is to test this. The pullup/pulldown circuit sitting prior to the input disconnect may be irrelevant here, but I would still test for feedthrough by slow ramping input voltages to io pins to be sure; the more pins tested simultaneously the bigger the feedthrough (if any, hopefully none). Of course if oodles of power are available then feedthrough may not really be an issue and can be ignored.

[Szabolcs]

Hugh, thank you for your insights.

Your measurements are consistent with the datasheet values, if we assume the pull-up/down resistors are 15K (11-16 by spec), then on all pins it yields a current of 3V/15K*32=6.4mA, just like you showed.

The pulling resistors being connected directly to the pin makes sense to me. For example. if you want an open-drain output, you would enable the pull-up resistor while disconnecting the input buffer. I agree that this is actually a mistake in the datasheet, the block diagram should show the connection of the pulling resistors, and the PIN[0].CNF.PULL register should be tied to them, not to the input buffer.