nRF5340 Timer / Counter Questions

I am developing a product which uses one nRF5340 Timer in timer mode and another in Counter mode. Reading through the nRF5340 Product Specification v1.6 I have the following questions:

In Section 7.53.3 it seems to imply that the TASKS_CLEAR event will not take effect if the timer is stopped. Is this true? If this is true does the clear occur as soon as the timer is started?

I am using a timer to publish periodic events. I am setting one CC register to the desired period and use a CLEAR shortcut on that CC register. In Section 7.53.4 seem to imply that if I am using a prescaler (counting at less than 16 MHz) I should load the CC register with the desired period. However, if I am running the timer at 16 MHz if I should use that the full period, or one less? If I do use the full period and do a counter capture at the last tick, do I get a 0 or the full period which was loaded into the CC register?

Section 7.35.5.19 includes a LowPowerCounter setting which is not discussed in the earlier sections. For spacing on the formatting of the "This enumerator is deprecated" suggests it should not be used. However, in the bitfield definitions in the file nrf5340_application_bitfields.h is the following:

/* Bits 1..0 : Timer mode */
#define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
#define TIMER_MODE_MODE_Msk (0x3UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
#define TIMER_MODE_MODE_Timer (0x0UL) /*!< Select Timer mode */
#define TIMER_MODE_MODE_Counter (0x1UL) /*!< Deprecated enumerator - Select Counter mode */
#define TIMER_MODE_MODE_LowPowerCounter (0x2UL) /*!< Select Low Power Counter mode */

Am I correct in assuming the comments for the TIMER_MODE_MODE_Counter value is incorrect and the TIMER_MODE_MODE_LowPowerCounter is the one deprecated?

Thank you

Parents
  • Hi Chip,

    In Section 7.53.3 it seems to imply that the TASKS_CLEAR event will not take effect if the timer is stopped. Is this true? If this is true does the clear occur as soon as the timer is started?

    No, as far as I know TASKS_CLEAR still take effect if the timer is stopped. Have you tried to test ? The sentence at 7.35.3 discusses about the guaranteed delay when the Timer is running. When the TIMER is not running it may take longer but it's not very important in my understanding as the Timer is stopped. 

    I am using a timer to publish periodic events. I am setting one CC register to the desired period and use a CLEAR shortcut on that CC register. In Section 7.53.4 seem to imply that if I am using a prescaler (counting at less than 16 MHz) I should load the CC register with the desired period. However, if I am running the timer at 16 MHz if I should use that the full period, or one less? If I do use the full period and do a counter capture at the last tick, do I get a 0 or the full period which was loaded into the CC register?

    My understanding is that the TIMER count is from 0 to full period -1. 

    Section 7.35.5.19 includes a LowPowerCounter setting which is not discussed in the earlier sections

    The LowPowerCounter mode is the mode when the HFCLK (16MHz) is not used for the timer until the COUNT task is triggered (only used for 1 clock cycle and then stop). It's actually the mode you should use as the inefficient "Counter" mode is deprecated. 

  • Thank you for the answers.

    On the last item, you mention that the LFCLK is when in low power counter mode instead of HFCLK. Does this imply that I will potentially miss counts if they are occurring faster than 32 kHz? (That would be an issue for my application.) Also are the capture events delayed until the next 32 kHz cycle?

    I will end up testing, at least the features I am planning on using.

    Thanks

Reply
  • Thank you for the answers.

    On the last item, you mention that the LFCLK is when in low power counter mode instead of HFCLK. Does this imply that I will potentially miss counts if they are occurring faster than 32 kHz? (That would be an issue for my application.) Also are the capture events delayed until the next 32 kHz cycle?

    I will end up testing, at least the features I am planning on using.

    Thanks

Children
  • Hi Chip, 
    I initially wrote about LFCLK but it was incorrect and have edited it right away but maybe it was too late. Sorry about that. 
    The information I got is that HFCLK is not keep running when you are using the TIMER in (low power) counter mode. It's only started for 1 clock cycle to increase the COUNTER when  you trigger TASK COUNT and then stop again after that. 

    Basically the "low power counter" is the default counter. When the "non low power" counter is deprecated (it was the only option on nRF51 series)

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