sQSPI: "High Speed Transfers" drive strength

[JordanYates]

The nRF54L porting guide (link) states that:

> High speed read transfers use hardware-enabled delay sampling and require resetting the pad configuration between reads. This applies to the entire port P2, which is important if you use other pins on this port in addition to those allocated for sQSPI. In this context, reset means first setting the drive strength to standard, then setting it back to extra high. When using sQSPI on the nRF54L Series devices, the Soft Peripheral must have exclusive access to extra-high-drive strength.

> no other peripheral or ETM trace on the P2 port can use the extra-high-drive GPIO configuration. They are limited to using high-drive strength

I wish to double check that "high-drive strength" for other peripherals is actually okay to use. It seems likely to me that resetting the entire P2 port to the standard drive strength would cause problems with a peripheral that is configured to use the high-drive strength. Wouldn't this behaviour result in the drive strength potentially resetting in the middle of a transaction?

[runsiv]

Hi Jordan. 
I will check this internally and will update as soon as I hear anything

Regards

Runar

[runsiv]

Update. Drive configuration is done in the DRIVE0/1 fields of the PIN_CNF GPIO register. It's a per-pin register. it does not apply to the entire port.

[JordanYates]

Does that mean that all of the text about the sQSPI requiring exclusive access to the extra-high-drive strength is incorrect? Other peripherals on P2 can also use the E0E1 strength?

[Kenneth]

Hello,

To configure extra high driver for the sqspi you do this in devicetree like this:

&pinctrl {
	sqspi_default: sqspi_default {
		group1 {
			psels = <NRF_PSEL(SDP_MSPI_SCK, 2, 1)>,
				<NRF_PSEL(SDP_MSPI_CS0, 2, 5)>,
				<NRF_PSEL(SDP_MSPI_DQ0, 2, 2)>;
			nordic,drive-mode = <NRF_DRIVE_E0E1>;
		};
		group2 {
			psels = <NRF_PSEL(SDP_MSPI_DQ1, 2, 4)>,
				<NRF_PSEL(SDP_MSPI_DQ2, 2, 3)>,
				<NRF_PSEL(SDP_MSPI_DQ3, 2, 0)>;
			nordic,drive-mode = <NRF_DRIVE_E0E1>;
			bias-pull-up;
		};
	};

	sqspi_sleep: sqspi_sleep {
		group1 {
			low-power-enable;
			psels = <NRF_PSEL(SDP_MSPI_SCK, 2, 1)>,
				<NRF_PSEL(SDP_MSPI_CS0, 2, 5)>,
				<NRF_PSEL(SDP_MSPI_DQ0, 2, 2)>,
				<NRF_PSEL(SDP_MSPI_DQ1, 2, 4)>,
				<NRF_PSEL(SDP_MSPI_DQ2, 2, 3)>,
				<NRF_PSEL(SDP_MSPI_DQ3, 2, 0)>;
		};
	};
};

Even though other pins can in theory also be configured to E0E1, please follow the statement from the documentation that says "...no other peripheral or ETM trace on the P2 port can use the extra-high-drive GPIO configuration. They are limited to using high-drive strength.."

Kenneth