: nRF Connect SDK 3.1.0 requires CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y – possible clock impact?

[Moh]

Hi,

I’m using NCS v3.1.0 and noticed that my application does not run unless I enable:

CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y

Without this configuration, the system fails to start.

However, when this option is enabled, I observe performance-related issues. Specifically, when reading large chunks of data from external flash and displaying them on an LCD, I see display corruption. Reducing the chunk size resolves the issue, which suggests a timing or clock-related problem.

The same project built on NCS v3.0.2 does not require this configuration and runs without any corruption issues.

Could this be related to LFCLK/HFCLK configuration changes in 3.1.0? What is the recommended way to properly configure the clock source in this version?

kind regards,

Moh

[Susheel Nuguru]

Hi Mohsin,

If your custom board lacks an external 32.768 kHz crystal then the behavior you see makes sense. You would then use the below config.

CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=n
CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y

This is a known requirement for custom boards without an LFXO. You should also ensure this is applied to all build images (MCUboot, ipc_radio if applicable), not just the main application, as missing it in a bootloader is a common cause of startup failures.

If your HFXO has a slow startup time, this could contribute to timing issues. If that is the case then try to increase CONFIG_MPSL_HFCLK_LATENCY. The release notes mention an increase in the default value to support slower crystals. For custom boards (non-DK), the default is 1400 in v3.1.0, whereas the DK uses a lower value based on measured crystal startup time. Can you please check the latency settings in your generated .config file and match it with what you XTAL requires to start? You need to use this setting in all of your configs including MCUBoot. 

[Moh]

Thanks. Susheel Nuguru Even after using

CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=n

CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y

CONFIG_CLOCK_CONTROL_NRF_K32SRC_500PPM=y

CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC_CALIBRATION=y

CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_LF_ALWAYS_ON=y

I don't see hfclk runs. I can see only on dbg

00> [00:00:00.000,124] <dbg> clock_control: clkstarted_handle: lfclk: Clock started

Any idea why?

[Moh]

Hi Susheel Nuguru  I have also noticed that image swap doesn't happen afer succesfully uplaod the image via Device Manager app. I am attaching the  project files as reference. I am using nRF54l15 MCU. Thankspoc.zip

[Susheel Nuguru]

In your project it seems like you set multiple LF sources at once.

poc/prj.conf:11 has CONFIG_CLOCK_CONTROL_NRF_K32SRC_SYNTH=y
poc/prj.conf:130 has CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y

If using RC, you need to have K32SRC_RC=y, K32SRC_XTAL=n, K32SRC_SYNTH=n 

If using XTAL, ensure board hardware/DTS oscillator config is correct, then set only XTAL.

Also, I hope you have proper HFCLK XTAL, Using RC oscillator for HFCLK is around 500 ppm which might still be inaccurate for high-speed QSPI transfers and display operations at the frequencies you are using. For that speeds of transfer you should be 

[Moh]

Thanks Susheel Nuguru . Pleae advise what I need to in dts file to make use of fast clock.

CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=nCONFIG_CLOCK_CONTROL_NRF_K32SRC_500PPM=n

CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC_CALIBRATION=n

CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_LF_ALWAYS_ON=n

CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=y

CONFIG_CLOCK_CONTROL_LOG_LEVEL_DBG=y
Poc_nrf54l15_cpuapp.dts

[Moh]

Also Susheel Nuguru , please confirm why the image doesn't get swapped after upload?

[Susheel Nuguru]

Hi, 

Moh said:

Also Susheel Nuguru , please confirm why the image doesn't get swapped after upload?

That is because in your poc/sysbuild/mcuboot/prj.conf, you have set CONFIG_BOOT_UPGRADE_ONLY=y. In this mode MCUboot does not do a swap style upgrade but an overwrite style upgrade. If you want the swap behavior then disable this config.