SPI master reconfigure on nRF54L15

Hi,

I have an application with 2 SPI IC connected to the same SPIM port of nRF54L15.

These 2 ICs have different SPI mode:

A: SPI Mode 1 (CPOL 0 CPHA 1)

B: SPI Mode 0 (CPOL 0 CPHA 0)

Should I reconfigure SPI before each communication? Like this post suggested (devzone.nordicsemi.com/.../spi-master-reconfigure)

And how should I modify drivers on ncs 3.2.3 to do that?

Regards,

Yuan Bo 

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  • Hi Yuan,

    The SPI mode is configured for each device on the bus individually. Do you have anything implemented already? If so, could you say a bit more about your current implementation. For example, if you are using the Zephyr SPI driver api directly from your application.

    Best regards,

    Vidar

  • Hi Vidar,

    My plan is using devicetree to define compatible spim devices like this (Not verified, may have some error):

    &spi21 {
        compatible = "nordic,nrf-spim";
        status = "okay";
        
        pinctrl-0 = <&spi21_default>;
        pinctrl-1 = <&spi21_sleep>;
        pinctrl-names = "default", "sleep";
    
        nucleo_nfc@0 {
            compatible = "x-nucleo-nfc";
            reg = <0>;
            spi-max-frequency = <DT_FREQ_M(8)>;
            irq-gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
            cs-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
        };
    
        gd25q32e: gd25q32e@0 {
            compatible = "nordic,spi-nor";
            reg = <0>;
            writeoc = "pp4o";
            readoc = "read4io";
            sck-frequency = <8000000>;
            label = "GD25Q32E";
            jedec-id = [c8 40 16];
            size = <33554432>;
            has-dpd;
            t-enter-dpd = <10000>;
            t-exit-dpd = <35000>;
            cs-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
        };
    };
    

    Regards,

    Yuan Bo

Reply
  • Hi Vidar,

    My plan is using devicetree to define compatible spim devices like this (Not verified, may have some error):

    &spi21 {
        compatible = "nordic,nrf-spim";
        status = "okay";
        
        pinctrl-0 = <&spi21_default>;
        pinctrl-1 = <&spi21_sleep>;
        pinctrl-names = "default", "sleep";
    
        nucleo_nfc@0 {
            compatible = "x-nucleo-nfc";
            reg = <0>;
            spi-max-frequency = <DT_FREQ_M(8)>;
            irq-gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
            cs-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
        };
    
        gd25q32e: gd25q32e@0 {
            compatible = "nordic,spi-nor";
            reg = <0>;
            writeoc = "pp4o";
            readoc = "read4io";
            sck-frequency = <8000000>;
            label = "GD25Q32E";
            jedec-id = [c8 40 16];
            size = <33554432>;
            has-dpd;
            t-enter-dpd = <10000>;
            t-exit-dpd = <35000>;
            cs-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
        };
    };
    

    Regards,

    Yuan Bo

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