Dear Nordic FAE Team,
I am currently developing a low-power Bluetooth product based on nRF54L10, and I have an urgent requirement to optimize the System OFF mode sleep current to ≤ 0.4 μA.
I fully understand that the official datasheet lists the typical System OFF current as 0.6 μA (no GRTC/LFXO, no RAM retention). However, I have verified that mass-produced products using nRF52832 can achieve an actual sleep current of around 0.4 μA, which is lower than its datasheet typical value.
Therefore, I would like to consult your official technical support for the ultimate low-power tuning guide of nRF54L10:
- Are there any hidden register configurations, power domain shutdown options, or unused peripheral hard disable methods to reduce the leakage current below 0.4 μA in System OFF mode?
- For PCB hardware design, are there ultra-low leakage layout specifications (such as unused pin processing, power filter matching, parasitic resistance suppression) that can cooperate with the chip to reduce static power consumption?
- Under extreme conditions (optimized voltage, temperature range), what is the practical mass-producible minimum System OFF current of nRF54L10? Do you have reference tuning cases or calibration steps?
Could you please provide the official internal tuning recommendations or engineering guidance? Your professional reply will be very helpful for our product mass production.
Thanks & Best Regards
