How to fix the voltage mismatch between VTref and VDD on the target board?

[Pony]

Hi everyone. I’m currently working on a custom board based on the nRF5340, but I’m unable to connect to the board when trying to flash it via the SWD interface using J-Link. Here is the error message from my SDK:

Error: One or more device info tasks failed:

302005664: Device error: A timeout occurred while handling debug power: Timed out trying to power sys and debug region

(Generic)

When troubleshooting with J-Link Commander, I got the following output:

J-Link>st

VTref=1.673V

ITarget=0mA

TCK=1 TDI=0 TDO=0 TMS=0 TRES=1 TRST=?

Supported target interface speeds:

• 96 MHz/n, (n>=24). => 4000kHz, 3840kHz, 3692kHz, ...

However, I measured 3.1V on the SWD VDD pin with a multimeter, and the main chip power supply seems normal.

Also, because I cannot connect, I cannot try the nrfjprog --recover command suggested by AI.

Does anyone have any good solutions?

[Kazi Afroza Sultana]

Hello,

Probably If VTref is not correctly connected to your board's VDD. As you can see 3.1V at VDD but on the Jlink commandar output Vterf is 1.6V. Can you check with different cable?

[Joao Colombari]

Hi Kazi, 

I have a few custom PCBs based on the nRF5340 and several peripheral ICs. One of these ICs has an absolute maximum supply voltage of 1.98 V. The boards do not include any external over-voltage protection.

For debugging, I have been using an nRF5340 DK as a J-Link probe, with SB19 shorted so that the probe senses the target VDD level.

Several boards eventually developed a hard short between VDD and GND. After some investigation, I found that the failed component was the IC with the 1.98 V maximum supply rating. Once it was removed, SWD access to the nRF5340 was restored.

Funny thing is that I have VTref = 3.3V log in the JLinkExe even if I measure 1.8V in the target. 

I have two questions: (i) when using the DK as a debugger in this configuration, is there any possibility that the probe could briefly drive or expose the target to a higher voltage (e.g., 3.3 V) before it detects and adapts to the target VDD level? And (ii) can I have such an output with such a target voltage? 

Best regards,

João Colombari

[Kazi Afroza Sultana]

Hello,

 (i) when using the DK as a debugger in this configuration, is there any possibility that the probe could briefly drive or expose the target to a higher voltage (e.g., 3.3 V) before it detects and adapts to the target VDD level?

"It is recommended to power the external board separately from the DK. The voltage on the external board must match that of the DK. When the DK is powered through the USB connector, the voltage is 3 V."

https://docs.nordicsemi.com/bundle/ug_nrf5340_dk/page/UG/dk/hw_debug_out_segger53.html#ariaid-title1 

I have not seen that we have done any characterizations on this. So, its best to power the custom board separately.

Thanks.

BR
Kazi

[Joao Colombari]

Thank you for the resconde.

My custom board is always powered separately, either by using a batery on the VBAT pin of the PMIC or by directly feeding 1V8 to the VDD pin. The DK is only used as a J-Link probe, with SB19 shorted.

However, I am still concerned about two observations:

1. JLinkExe reports VTref = 3.3 V, while a direct measurement on the target VDD/VTref rail shows approximately 1.8 V.
2. I do not know whether the DK/J-Link may briefly drive the SWD lines at a higher voltage before VTref is detected and the I/O levels are adjusted.

Could you please clarify:

• Is the VTref value reported by JLinkExe measured directly from the VTref pin on the target, or can it reflect an internal voltage on the DK under some conditions?
• If VTref is incorrectly detected as 3.3 V, could the SWD signals be driven at 3.3 V?
• Has Nordic or SEGGER characterized the behavior of the SWD pins during probe connection or reset, specifically before VTref detection is completed?

The reason I ask is that several boards failed in a similar manner, and the failed component was an IC with an absolute maximum supply voltage of 1.98 V. Therefore, I am trying to determine whether an overvoltage event through the debug interface could be a possible failure mechanism.

Thank you for your help.

[Joao Colombari]

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