How to fix the voltage mismatch between VTref and VDD on the target board?

[Pony]

Hi everyone. I’m currently working on a custom board based on the nRF5340, but I’m unable to connect to the board when trying to flash it via the SWD interface using J-Link. Here is the error message from my SDK:

Error: One or more device info tasks failed:

302005664: Device error: A timeout occurred while handling debug power: Timed out trying to power sys and debug region

(Generic)

When troubleshooting with J-Link Commander, I got the following output:

J-Link>st

VTref=1.673V

ITarget=0mA

TCK=1 TDI=0 TDO=0 TMS=0 TRES=1 TRST=?

Supported target interface speeds:

• 96 MHz/n, (n>=24). => 4000kHz, 3840kHz, 3692kHz, ...

However, I measured 3.1V on the SWD VDD pin with a multimeter, and the main chip power supply seems normal.

Also, because I cannot connect, I cannot try the nrfjprog --recover command suggested by AI.

Does anyone have any good solutions?

[Joao Colombari]

Thank you for the resconde.

My custom board is always powered separately, either by using a batery on the VBAT pin of the PMIC or by directly feeding 1V8 to the VDD pin. The DK is only used as a J-Link probe, with SB19 shorted.

However, I am still concerned about two observations:

1. JLinkExe reports VTref = 3.3 V, while a direct measurement on the target VDD/VTref rail shows approximately 1.8 V.
2. I do not know whether the DK/J-Link may briefly drive the SWD lines at a higher voltage before VTref is detected and the I/O levels are adjusted.

Could you please clarify:

• Is the VTref value reported by JLinkExe measured directly from the VTref pin on the target, or can it reflect an internal voltage on the DK under some conditions?
• If VTref is incorrectly detected as 3.3 V, could the SWD signals be driven at 3.3 V?
• Has Nordic or SEGGER characterized the behavior of the SWD pins during probe connection or reset, specifically before VTref detection is completed?

The reason I ask is that several boards failed in a similar manner, and the failed component was an IC with an absolute maximum supply voltage of 1.98 V. Therefore, I am trying to determine whether an overvoltage event through the debug interface could be a possible failure mechanism.

Thank you for your help.

[Joao Colombari]

Typo: response*

[Kazi Afroza Sultana]

Hello,

''

• Is the VTref value reported by JLinkExe measured directly from the VTref pin on the target, or can it reflect an internal voltage on the DK under some conditions?
• If VTref is incorrectly detected as 3.3 V, could the SWD signals be driven at 3.3 V?''

There is no built-in level shifter for the on-board debugger so it will not adjust the Input-output (IO) voltage based on the Vterf voltage. The IO voltage of the DK must match the IO voltage on the target for this reason what I mentioned in the previous reply also.

To power the 1.8V custom board from nRF5340 DK, you can follow the steps mentioned below:

1. Connect a USB to both J2 and J3 (nRF USB port)

2. On the SW9, switch from ''VDD'' to ''USB''

3. Power up the DK

Then you can get 1.8V from the debugger.

Thanks.

BR
Kazi

[Felipe Pimenta]

Hello Kazi,

I am a colleague of João working on the same board. I would like to clarify a few things.

There seems to be some conflicting information about the purpose of the SB19 and the ability of the nRF5340 DK to drop the VDD level to 1.8 V based on the VIO_REF level supplied by an external board.

The nRF5340 DK User Guide does not mention this, and some answers here on DevZone suggest it's not possible. However, some answers suggest it is possible. More specifically, in https://devzone.nordicsemi.com/f/nordic-q-a/115349/programming-external-mcu-with-nrf5340-dk this is clearly stated as being possible, while in https://devzone.nordicsemi.com/f/nordic-q-a/104739/i-can-t-program-external-board-with-nrf5340-2-0-2/450783 it is even acknowledged that this information is missing from the DK User Guide.

We have tested and confirmed this behavior a few months ago, and have been using the DK this way to program and debug our custom boards since then.

As João stated, some of our boards have presented some issues related to this IC he described, which has a maximum supply voltage of 1.98 V. We are not using the DK to supply power to our custom board. It is being powered separately. Our question is if this behavior of dropping VDD based on VIO_REF (which we confirmed to be true) could have some sort of delay and, therefore, could briefly expose this IC to a voltage over its limit.

Thanks.

Felipe.