On the nRF54LM20A, can the CPU operate normally while RRAM is undergoing read, write, or erase operations?

[Liny]

On the previous nRF52833, the CPU cannot function normally during flash write or erase operations.

With the nRF54 series upgraded to RRAM, does a similar limitation still exist? Specifically, during RRAM read, write, or erase operations, can the CPU continue to run normally, and can interrupts be handled as expected?

I don't quite understand the statement that whether the CPU will halt depends on the source of the code. How should this be explained, and could you provide some examples?
Thanks!

[tesc]

Hi,

If an instruction is to be fetched from RRAM while the RRAM is busy with writing or other operations, then the CPU will halt until RRAM is available again.

The CPU will not halt if the instruction is hit in the cache, or if running from SRAM.

Halting behavior is the same for interrupt routines, i.e. cache misses when running from RRAM always may lead to delay (when RRAM is busy at the moment.)

See also the Memory and other chapters of the nRF54LM20A Datasheet. The term "Product Specification" was previously used for our Datasheets, which is why the term is still seen some places also in SDK documentation.

Regards,
Terje