Theoretical vs. Practical Limits of AHB Multi-Mastery pair number (nRF5340)

[gwan0624]

There expect to be a physical limit to the number of components an AHB can support.

For instance, if 8 different masters (Including App core, Net core, several peripherals's DMA master, etc) attempt to access 8 different RAMs simultaneously, one might theoretically expect 8 master-slave pairs to be active at once.

However, what is the reality of this in a practical implementation?

I think 5 pair (net core, CBus, SBus, two DMA master) is limit, but I'm not sure

[Einar Thorsrud]

Hi,

This mostly makes sense. An additional AHB master is CryptoCell (CC312). Also, note the recommendations to avoid AHB bus contention and the priorities listed under the AHB multilayer documentation for the app core (and here for the net core).

[gwan0624]

So, are you saying the maximum is 5?

Or do you mean there’s no limit to the number of AHB [layers/masters] that can operate simultaneously, as long as different masters aren't sharing the same slave? (But is there actually enough physical wiring prepared for that many AHB connections?)

[Einar Thorsrud]

The latter. I am not able to see a hard maximum limit of concurrent masters. The practical limitations is described in the documentation I linked to in my previous post.