Hi,
I am working on a project that requires high quality audio capture and wireless transmission using two nRF5340-DK boards running the nRF5340 Audio application (NCS v3.2.1). The BLE LE Audio CIS pipeline is fully working, LC3 at 24kHz with zero packet loss. The remaining challenge is getting clean audio into the pipeline on the transmitter side.
I have gone through several approaches and hit a wall with each one. Posting here in case someone has found a working path I have not tried yet.
PDM microphone (internal peripheral): The nRF5340 PDM hardware is limited to 1.333 MHz clock maximum. This is too low for good audio quality. The resulting audio is muffled and heavily low-frequency biased. I confirmed this is a hardware limit and not configurable in software.
I2S microphone (INMP441, nRF5340 as I2S master): The nRF5340 generates the wrong sample rate. With HFCLKAUDIO at 12.288 MHz and any integer ratio, the actual LRCK comes out at approximately 26.666 kHz instead of 24 kHz. This is a known integer division issue with the ACLK. The audio is pitch-shifted and distorted and I could not find a ratio that lands exactly on 24 kHz.
External I2S ADC with analog microphone (PCM1808, nRF5340 as I2S master, ADC as slave): This is the approach I am currently testing, lowering the sample rate to 16 kHz to reduce clock stress. BCK and LRCK look correct on the oscilloscope. The problem is SCKI, the MCK output on P1.08, which comes out as a distorted sinusoid between 0.5V and 2.5V instead of a clean logic square wave. The PCM1808 requires a valid SCKI to exit power-down and raise VREF to 2.5V. VREF stays at 0V, meaning the chip never starts up. I am planning to add a 74LVC1G04 buffer between P1.08 and the ADC SCKI pin to fix the signal level, but I have not received the component yet.
My questions:
1. Is the sinusoidal MCK output on P1.08 expected behavior on the nRF5340-DK? Is there a drive strength or clock bypass configuration that produces a cleaner logic signal at that pin?
2. For the I2S microphone approach, is there any way to configure the nRF5340 I2S master to produce exactly 24 kHz LRCK with HFCLKAUDIO at 12.288 MHz? Or is the integer division limitation confirmed and unavoidable?
3. For the PDM approach, is there any path to increase the PDM clock beyond 1.333 MHz on the nRF5340, or is that a hard silicon limit?
4. Has anyone successfully captured good quality audio on a standard nRF5340-DK and fed it into the nRF5340 Audio pipeline? Any working configuration would be helpful.
Thanks.
