GRTC after reset

[omt]

Hi,

I am developing an application for the nRF54L15 using NCS v3.2.4, running entirely in the Secure domain.

My goal is to maintain a continuous hardware system time that survives external hardware resets, specifically a Pin Reset , WDT reset

According to the nRF54L15 Product Specification, the GRTC resides in the Always-On (AON) power domain and its SYSCOUNTER should not be wiped by a Pin Reset.

However, I am experiencing behavior where the counter appears to be zeroed out or masked during boot. To investigate, I implemented a custom hook using SYS_INIT() at different initialization levels to read the GRTC counter via nrf_grtc_sys_counter_get(NRF_GRTC).

Here are the exact results I am seeing after an SWD flash/Pin Reset:

1. At PRE_KERNEL_1 (priority 0): The function consistently returns a stable, repeatable 89 µs (hex 0x59). This indicates that the counter has either just been cleared or a software offset was applied exactly 89 microseconds before my hook executed.

2. At EARLY (priority 0): The function returns exactly 4611686018427387904 (which is hex 0x4000000000000000). This means bit 62 is set, which I suspect is a hardware status flag indicating that the fast CPU clock domain (SYSCLK) is not yet synchronized with the slow Always-On domain (LFCLK) of the GRTC.

 Is it possible to use GRTC as a continuous, reset-surviving hardware counter (except POR)?